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Commit ac45ea83 authored by BAZIN Jean-Noel's avatar BAZIN Jean-Noel
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Update incomplete VHDL sources

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src/adrgenUnit.vhd
+ 20
− 20
View file @ ac45ea83
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity adrgenUnit is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
I_clr_PtrLine : in STD_LOGIC;
I_inc_PtrLine : in STD_LOGIC;
I_clr_PtrCol : in STD_LOGIC;
I_inc_PtrCol : in STD_LOGIC;
I_selPix : in STD_LOGIC_VECTOR (1 downto 0);
O_EndImage : out STD_LOGIC;
O_NewLine : out STD_LOGIC;
O_ADR_R : out STD_LOGIC_VECTOR (13 downto 0); -- La profondeur de la mémoire IN = 100x100 = 10000
O_ADR_W : out STD_LOGIC_VECTOR (13 downto 0) -- La profondeur de la mémoire OUT = 100x100 = 10000
port (
I_clk : in std_logic;
I_clr_PtrLine : in std_logic;
I_inc_PtrLine : in std_logic;
I_clr_PtrCol : in std_logic;
I_inc_PtrCol : in std_logic;
I_selPix : in std_logic_vector (1 downto 0);
O_EndImage : out std_logic;
O_NewLine : out std_logic;
O_ADR_R : out std_logic_vector (13 downto 0); -- La profondeur de la mémoire IN = 100x100 = 10000
O_ADR_W : out std_logic_vector (13 downto 0) -- La profondeur de la mémoire OUT = 100x100 = 10000
);
end adrgenUnit;
architecture Behavioral of adrgenUnit is
-- déclaration des signaux internes
_BLANK_
--
-- Write here your VHDL code
--
begin
_BLANK_
--
-- Write here your VHDL code
--
end Behavioral;
src/automate.vhd
+ 123
− 137
View file @ ac45ea83
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.all;
-----------------------------------------------------
entity automate is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
I_go : in STD_LOGIC;
I_EndImage : in STD_LOGIC;
I_NewLine : in STD_LOGIC;
port (
I_clk : in std_logic;
I_rst : in std_logic;
I_go : in std_logic;
I_EndImage : in std_logic;
I_NewLine : in std_logic;
-- signaux de commandes vers l'unit oprative
O_ldPix11 : out STD_LOGIC;
O_ldPix21 : out STD_LOGIC;
O_ldPix31 : out STD_LOGIC;
O_shReg : out STD_LOGIC;
O_ldPixEdge : out STD_LOGIC;
O_ldPix11 : out std_logic;
O_ldPix21 : out std_logic;
O_ldPix31 : out std_logic;
O_shReg : out std_logic;
O_ldPixEdge : out std_logic;
-- signaux de commandes vers le gnrateur d'adresses
O_clr_PtrLine : out STD_LOGIC;
O_inc_PtrLine : out STD_LOGIC;
O_clr_PtrCol : out STD_LOGIC;
O_inc_PtrCol : out STD_LOGIC;
O_selPix : out STD_LOGIC_VECTOR (1 downto 0);
O_clr_PtrLine : out std_logic;
O_inc_PtrLine : out std_logic;
O_clr_PtrCol : out std_logic;
O_inc_PtrCol : out std_logic;
O_selPix : out std_logic_vector (1 downto 0);
-- signaux de commandes vers les mmoires
O_enM_R : out STD_LOGIC;
O_enM_W : out STD_LOGIC;
O_enM_R : out std_logic;
O_enM_W : out std_logic;
-- signal de commande vers le contrleur VGA
O_StartDisplay : out STD_LOGIC
O_StartDisplay : out std_logic
);
end automate;
-----------------------------------------------------
architecture Behavioral of automate is
......@@ -41,19 +39,19 @@ signal current_state, next_state : automate_state_type := Idle;
begin
-- Le registre d'tat
state_reg: process(_BLANK_TO_FILL_)
state_reg : process(I_clk)
begin
if (reset='1') then -- asynchronous reset (active high)
if (rising_edge(I_clk)) then
if (I_rst = '1') then
current_state <= Idle;
elsif (clk'event and clk='1') then -- rising edge of clk
else
current_state <= next_state;
end if;
end if;
end process state_reg;
-- Calcul de l'tat suivant et des sorties
comb_logic: process(_BLANK_TO_FILL_)
comb_logic : process(current_state, I_go, I_EndImage, I_NewLine)
begin
-- initialisation de TOUTES les sorties
O_ldPix11 <= '0';
......@@ -91,7 +89,11 @@ begin
O_selPix <= "00";
-- calcul de l'tat suivant
if(I_EndImage = '0') then
next_state <= Pix1;
else
next_state <= EndSobel;
end if;
when Pix1 =>
-- calcul des sorties SPECIFIQUES l'tat
......@@ -100,38 +102,22 @@ begin
O_selPix <= "01";
-- calcul de l'tat suivant
if(I_EndImage = '0') then
next_state <= Pix2;
else
next_state <= EndSobel;
end if;
when Pix2 =>
-- calcul des sorties SPECIFIQUES l'tat
__BLANK_TO_FILL__
-- calcul de l'tat suivant
next_state <= __BLANK_TO_FILL__
__BLANK_TO_FILL__
--
-- Write here your VHDL code
--
when others =>
next_state <= Idle;
when others => Idle;
end case;
end process comb_logic;
end Behavioral;
src/gradientUnit.vhd
+ 13
− 14
View file @ ac45ea83
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity gradientUnit is
Port ( I_Pix11, I_Pix12, I_Pix13 : in STD_LOGIC_VECTOR (7 downto 0);
I_Pix21, I_Pix22, I_Pix23 : in STD_LOGIC_VECTOR (7 downto 0);
I_Pix31, I_Pix32, I_Pix33 : in STD_LOGIC_VECTOR (7 downto 0);
O_pixEdge : out STD_LOGIC
port (I_Pix11, I_Pix12, I_Pix13 : in std_logic_vector (7 downto 0);
I_Pix21, I_Pix22, I_Pix23 : in std_logic_vector (7 downto 0);
I_Pix31, I_Pix32, I_Pix33 : in std_logic_vector (7 downto 0);
O_pixEdge : out std_logic
);
end gradientUnit;
architecture Behavioral of gradientUnit is
-- déclaration des signaux internes
_BLANK_
--
-- Write here your VHDL code
--
begin
_BLANK_
--
-- Write here your VHDL code
--
end Behavioral;
src/pixedgeReg.vhd
+ 15
− 17
View file @ ac45ea83
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pixedgeReg is
Port ( clk :in STD_LOGIC;
reset :in STD_LOGIC;
I_pixEdge : in STD_LOGIC;
I_ldPixEdge : in STD_LOGIC;
O_pixEdge : out STD_LOGIC
port (
I_clk : in std_logic;
I_pixEdge : in std_logic;
I_ldPixEdge : in std_logic;
O_pixEdge : out std_logic
);
end pixedgeReg;
architecture Behavioral of pixedgeReg is
-- déclaration des signaux internes
_BLANK_
--
-- Write here your VHDL code
--
begin
_BLANK_
--
-- Write here your VHDL code
--
end Behavioral;
src/regUnit.vhd
+ 36
− 51
View file @ ac45ea83
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity regUnit is
Port ( clk :in STD_LOGIC;
reset :in STD_LOGIC;
I_pixel : in STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
I_ldPix11 : in STD_LOGIC;
I_ldPix21 : in STD_LOGIC;
I_ldPix31 : in STD_LOGIC;
I_shReg : in STD_LOGIC;
O_Pix11, O_Pix12, O_Pix13 : out STD_LOGIC_VECTOR (7 downto 0);
O_Pix21, O_Pix22, O_Pix23 : out STD_LOGIC_VECTOR (7 downto 0);
O_Pix31, O_Pix32, O_Pix33 : out STD_LOGIC_VECTOR (7 downto 0)
port (I_clk : in std_logic;
I_pixel : in std_logic_vector (7 downto 0); -- Pixel from the memory
I_ldPix11 : in std_logic;
I_ldPix21 : in std_logic;
I_ldPix31 : in std_logic;
I_shReg : in std_logic;
O_Pix11, O_Pix12, O_Pix13 : out std_logic_vector (7 downto 0);
O_Pix21, O_Pix22, O_Pix23 : out std_logic_vector (7 downto 0);
O_Pix31, O_Pix32, O_Pix33 : out std_logic_vector (7 downto 0)
);
end regUnit;
architecture Behavioral of regUnit is
signal S_Pix11, S_Pix12, S_Pix13 : STD_LOGIC_VECTOR (7 downto 0);
signal S_Pix21, S_Pix22, S_Pix23 : STD_LOGIC_VECTOR (7 downto 0);
signal S_Pix31, S_Pix32, S_Pix33 : STD_LOGIC_VECTOR (7 downto 0);
signal S_Pix11, S_Pix12, S_Pix13 : std_logic_vector (7 downto 0) := (others => '0');
signal S_Pix21, S_Pix22, S_Pix23 : std_logic_vector (7 downto 0) := (others => '0');
signal S_Pix31, S_Pix32, S_Pix33 : std_logic_vector (7 downto 0) := (others => '0');
begin
-- banc de registres
process(_BLANK_)
process(I_clk)
begin
if(reset = '1') then
S_Pix11 <= (others => '0');
S_Pix12 <= (others => '0');
S_Pix13 <= (others => '0');
S_Pix21 <= (others => '0');
S_Pix22 <= (others => '0');
S_Pix23 <= (others => '0');
S_Pix31 <= (others => '0');
S_Pix32 <= (others => '0');
S_Pix33 <= (others => '0');
elsif(rising_edge(clk)) then
if(rising_edge(I_clk)) then
_BLANK_
--
-- Write here your VHDL code
--
end if;
end process;
-- Connecter les sorties des registres aux ports
-- d’entrée/sortie du banc de registres
O_Pix11 <= S_Pix11;
O_Pix12 <= S_Pix12;
O_Pix13 <= S_Pix13;
......@@ -61,4 +47,3 @@ begin
O_Pix33 <= S_Pix33;
end Behavioral;
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