diff --git a/src/adrgenUnit.vhd b/src/adrgenUnit.vhd
index c430557553b0bf963350c778e473cb8da9835c70..04a955337c5103fb4d37978ccf04fbfd7b2d8734 100644
--- a/src/adrgenUnit.vhd
+++ b/src/adrgenUnit.vhd
@@ -1,35 +1,35 @@
 
 library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
 
 
 entity adrgenUnit is
-    Port ( clk	 		 : in STD_LOGIC;
-		   reset	 	 : in STD_LOGIC;
-		   I_clr_PtrLine : in STD_LOGIC;
-		   I_inc_PtrLine : in STD_LOGIC;
-		   I_clr_PtrCol  : in STD_LOGIC;
-		   I_inc_PtrCol  : in STD_LOGIC;
-		   I_selPix 	 : in STD_LOGIC_VECTOR (1 downto 0);
-		   O_EndImage	 : out STD_LOGIC;
-		   O_NewLine	 : out STD_LOGIC;
-		   O_ADR_R		 : out STD_LOGIC_VECTOR (13 downto 0); -- La profondeur de la mémoire IN = 100x100 = 10000
-		   O_ADR_W	 	 : out STD_LOGIC_VECTOR (13 downto 0)  -- La profondeur de la mémoire OUT = 100x100 = 10000   
-		   ); 
+    port (
+        I_clk         : in  std_logic;
+        I_clr_PtrLine : in  std_logic;
+        I_inc_PtrLine : in  std_logic;
+        I_clr_PtrCol  : in  std_logic;
+        I_inc_PtrCol  : in  std_logic;
+        I_selPix      : in  std_logic_vector (1 downto 0);
+        O_EndImage    : out std_logic;
+        O_NewLine     : out std_logic;
+        O_ADR_R       : out std_logic_vector (13 downto 0);  -- La profondeur de la mémoire IN = 100x100 = 10000
+        O_ADR_W       : out std_logic_vector (13 downto 0)   -- La profondeur de la mémoire OUT = 100x100 = 10000
+        );
 end adrgenUnit;
 
 
 architecture Behavioral of adrgenUnit is
 
--- déclaration des signaux internes
-	_BLANK_
+--
+-- Write here your VHDL code
+--
 
 begin
 
-	
-	_BLANK_
-		
+--
+-- Write here your VHDL code
+--
 
 end Behavioral;
-
diff --git a/src/automate.vhd b/src/automate.vhd
index 11109c126977cb2562bc0f594d2175e0ac16c878..affac4b059f1651ec2a17d20c278fc7623bb4e10 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -1,137 +1,123 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
------------------------------------------------------
-entity automate is
-    Port ( clk			 : in STD_LOGIC;
-		   reset		 : in STD_LOGIC;
-		   I_go	   		 : in STD_LOGIC;
-		   I_EndImage	 : in STD_LOGIC;
-		   I_NewLine	 : in STD_LOGIC;
-		   -- signaux de commandes vers l'unit� op�rative
-           O_ldPix11 	 : out  STD_LOGIC;
-           O_ldPix21 	 : out  STD_LOGIC;
-           O_ldPix31 	 : out  STD_LOGIC;
-           O_shReg 		 : out  STD_LOGIC;
-		   O_ldPixEdge 	 : out STD_LOGIC;
-		   -- signaux de commandes vers le g�n�rateur d'adresses		   
-		   O_clr_PtrLine : out STD_LOGIC;
-		   O_inc_PtrLine : out STD_LOGIC;
-		   O_clr_PtrCol  : out STD_LOGIC;
-		   O_inc_PtrCol  : out STD_LOGIC;
-		   O_selPix 	 : out STD_LOGIC_VECTOR (1 downto 0);		   
-		   -- signaux de commandes vers les m�moires		   
-		   O_enM_R		 : out STD_LOGIC;
-		   O_enM_W		 : out STD_LOGIC;
-		   -- signal de commande vers le contr�leur VGA		   		   
-		   O_StartDisplay  : out STD_LOGIC		   
-		   ); 
-end automate;
------------------------------------------------------
-
-
-architecture Behavioral of automate is
-
--- d�finir un type �num�r� avec les �tats de la FSM et deux signaux de ce type
-type automate_state_type is (Idle, Init, Pix1, Pix2, Pix3, sh1, Pix4, Pix5, 
-							 Pix6, sh2, Pix7, Pix8, Pix9, Exec, OutEdge, 
-							 sh3, EndSobel);
-signal current_state, next_state : automate_state_type := Idle;
-  
-begin
-
--- Le registre d'�tat
-state_reg: process(_BLANK_TO_FILL_)
-begin
-	if (reset='1') then  				-- asynchronous reset (active high)
-        current_state <= Idle;
-	elsif (clk'event and clk='1') then	-- rising edge of clk
-	    current_state <= next_state;
-	end if;
-end process state_reg;
-
-	
--- Calcul de l'�tat suivant et des sorties
-comb_logic: process(_BLANK_TO_FILL_)
-begin
-	-- initialisation de TOUTES les sorties
-    O_ldPix11		<= '0';
-    O_ldPix21 	    <= '0';
-    O_ldPix31 	    <= '0';
-    O_shReg 		<= '0'; 
-	O_ldPixEdge 	<= '0'; 
-	O_clr_PtrLine   <= '0';
-	O_inc_PtrLine   <= '0';
-	O_clr_PtrCol    <= '0';
-	O_inc_PtrCol    <= '0';
-	O_selPix 	 	<= "00";   
-	O_enM_R		    <= '0';
-	O_enM_W		    <= '0';
-	O_StartDisplay	<= '0';
-	next_state		<= Idle;
-	
-	case current_state is
-
-		when Idle =>			
-				-- calcul des sorties SPECIFIQUES � l'�tat
-				O_clr_PtrLine	<= I_go;
-				O_clr_PtrCol	<= I_go;
-				
-				-- calcul de l'�tat suivant
-				if(I_go = '1') then
-					next_state	<= Init;
-				else
-					next_state	<= Idle;
-				end if;
-
-		when Init =>			
-				-- calcul des sorties SPECIFIQUES � l'�tat
-				O_enM_R		<= '1';
-				O_selPix	<= "00";
-				
-				-- calcul de l'�tat suivant
-				next_state	<= Pix1;
-
-		when Pix1 =>			
-				-- calcul des sorties SPECIFIQUES � l'�tat
-				O_ldPix11	<= '1';
-				O_enM_R		<= '1';
-				O_selPix	<= "01";
-				
-				-- calcul de l'�tat suivant
-				if(I_EndImage = '0') then
-					next_state	<= Pix2;
-				else
-					next_state	<= EndSobel;
-				end if;
-				
-		when Pix2 => 
-				-- calcul des sorties SPECIFIQUES � l'�tat
-				__BLANK_TO_FILL__
-				
-				-- calcul de l'�tat suivant
-				next_state	<= __BLANK_TO_FILL__	
-		
-
-		
-		
-
-		
-		
-		__BLANK_TO_FILL__
-			
-
-
-
-			
-			
-	    when others =>	
-				next_state	<= Idle;
-	end case;
-end process comb_logic;
-	
-end Behavioral;
-
-
-
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity automate is
+    port (
+        I_clk          : in  std_logic;
+        I_rst          : in  std_logic;
+        I_go           : in  std_logic;
+        I_EndImage     : in  std_logic;
+        I_NewLine      : in  std_logic;
+        -- signaux de commandes vers l'unit� op�rative
+        O_ldPix11      : out std_logic;
+        O_ldPix21      : out std_logic;
+        O_ldPix31      : out std_logic;
+        O_shReg        : out std_logic;
+        O_ldPixEdge    : out std_logic;
+        -- signaux de commandes vers le g�n�rateur d'adresses
+        O_clr_PtrLine  : out std_logic;
+        O_inc_PtrLine  : out std_logic;
+        O_clr_PtrCol   : out std_logic;
+        O_inc_PtrCol   : out std_logic;
+        O_selPix       : out std_logic_vector (1 downto 0);
+        -- signaux de commandes vers les m�moires
+        O_enM_R        : out std_logic;
+        O_enM_W        : out std_logic;
+        -- signal de commande vers le contr�leur VGA
+        O_StartDisplay : out std_logic
+        );
+end automate;
+
+architecture Behavioral of automate is
+
+-- d�finir un type �num�r� avec les �tats de la FSM et deux signaux de ce type
+    type automate_state_type is (Idle, Init, Pix1, Pix2, Pix3, sh1, Pix4, Pix5,
+                                 Pix6, sh2, Pix7, Pix8, Pix9, Exec, OutEdge,
+                                 sh3, EndSobel);
+    signal current_state, next_state : automate_state_type := Idle;
+
+begin
+
+    state_reg : process(I_clk)
+    begin
+        if (rising_edge(I_clk)) then
+            if (I_rst = '1') then
+                current_state <= Idle;
+            else
+                current_state <= next_state;
+            end if;
+        end if;
+    end process state_reg;
+
+
+    comb_logic : process(current_state, I_go, I_EndImage, I_NewLine)
+    begin
+        -- initialisation de TOUTES les sorties
+        O_ldPix11      <= '0';
+        O_ldPix21      <= '0';
+        O_ldPix31      <= '0';
+        O_shReg        <= '0';
+        O_ldPixEdge    <= '0';
+        O_clr_PtrLine  <= '0';
+        O_inc_PtrLine  <= '0';
+        O_clr_PtrCol   <= '0';
+        O_inc_PtrCol   <= '0';
+        O_selPix       <= "00";
+        O_enM_R        <= '0';
+        O_enM_W        <= '0';
+        O_StartDisplay <= '0';
+        next_state     <= Idle;
+
+        case current_state is
+
+            when Idle =>
+                -- calcul des sorties SPECIFIQUES � l'�tat
+                O_clr_PtrLine <= I_go;
+                O_clr_PtrCol  <= I_go;
+
+                -- calcul de l'�tat suivant
+                if(I_go = '1') then
+                    next_state <= Init;
+                else
+                    next_state <= Idle;
+                end if;
+
+            when Init =>
+                -- calcul des sorties SPECIFIQUES � l'�tat
+                O_enM_R  <= '1';
+                O_selPix <= "00";
+
+                -- calcul de l'�tat suivant
+                if(I_EndImage = '0') then
+                    next_state <= Pix1;
+                else
+                    next_state <= EndSobel;
+                end if;
+
+            when Pix1 =>
+                -- calcul des sorties SPECIFIQUES � l'�tat
+                O_ldPix11 <= '1';
+                O_enM_R   <= '1';
+                O_selPix  <= "01";
+
+                -- calcul de l'�tat suivant
+                next_state <= Pix2;
+
+            when Pix2 =>
+
+
+
+
+--
+-- Write here your VHDL code
+--
+
+
+
+
+            when others => Idle;
+        end case;
+    end process comb_logic;
+
+end Behavioral;
diff --git a/src/gradientUnit.vhd b/src/gradientUnit.vhd
index 3def2d746e73b80d0b098a739e81dc9813742b1d..9619d8e55e61d10a4d5a3a520a5c368a29e9fffe 100644
--- a/src/gradientUnit.vhd
+++ b/src/gradientUnit.vhd
@@ -1,28 +1,27 @@
 
 library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
 
 entity gradientUnit is
-    Port ( I_Pix11, I_Pix12, I_Pix13 : in STD_LOGIC_VECTOR (7 downto 0);
-		   I_Pix21, I_Pix22, I_Pix23 : in STD_LOGIC_VECTOR (7 downto 0);
-		   I_Pix31, I_Pix32, I_Pix33 : in STD_LOGIC_VECTOR (7 downto 0);
-		   O_pixEdge : out  STD_LOGIC		   
-		   ); 
+    port (I_Pix11, I_Pix12, I_Pix13 : in  std_logic_vector (7 downto 0);
+          I_Pix21, I_Pix22, I_Pix23 : in  std_logic_vector (7 downto 0);
+          I_Pix31, I_Pix32, I_Pix33 : in  std_logic_vector (7 downto 0);
+          O_pixEdge                 : out std_logic
+          );
 end gradientUnit;
 
 
 architecture Behavioral of gradientUnit is
 
--- déclaration des signaux internes
-	_BLANK_
+--
+-- Write here your VHDL code
+--
 
 begin
 
-	
-	_BLANK_
-		
+--
+-- Write here your VHDL code
+--
 
 end Behavioral;
-
diff --git a/src/pixedgeReg.vhd b/src/pixedgeReg.vhd
index af5e3f636d7f8a9eb391b853b0ea7863993072be..3fdce0a76732f4c093d157ced909bdf305b5d3ab 100644
--- a/src/pixedgeReg.vhd
+++ b/src/pixedgeReg.vhd
@@ -1,29 +1,27 @@
 
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 entity pixedgeReg is
-    Port ( clk			:in STD_LOGIC;
-		   reset		:in STD_LOGIC;
-		   I_pixEdge : in  STD_LOGIC;
-		   I_ldPixEdge : in STD_LOGIC;
-		   O_pixEdge : out  STD_LOGIC		   
-		   ); 
+    port (
+        I_clk       : in  std_logic;
+        I_pixEdge   : in  std_logic;
+        I_ldPixEdge : in  std_logic;
+        O_pixEdge   : out std_logic
+        );
 end pixedgeReg;
 
-
 architecture Behavioral of pixedgeReg is
 
--- déclaration des signaux internes
-	_BLANK_
+--
+-- Write here your VHDL code
+--
 
 begin
 
-	
-	_BLANK_
-		
+--
+-- Write here your VHDL code
+--
 
 end Behavioral;
-
diff --git a/src/regUnit.vhd b/src/regUnit.vhd
index 2ecd3a2892ec847d1f36dbcf7f60d4c4312d7cf8..4f30b476b72c6fe5a6f8466fa278ca76d4507b76 100644
--- a/src/regUnit.vhd
+++ b/src/regUnit.vhd
@@ -1,64 +1,49 @@
 
 library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
 
 entity regUnit is
-    Port ( clk			:in STD_LOGIC;
-	       reset		:in STD_LOGIC;
-		   I_pixel : in  STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
-           I_ldPix11 : in  STD_LOGIC;
-           I_ldPix21 : in  STD_LOGIC;
-           I_ldPix31 : in  STD_LOGIC;
-           I_shReg : in  STD_LOGIC;
-		   O_Pix11, O_Pix12, O_Pix13 : out STD_LOGIC_VECTOR (7 downto 0);
-		   O_Pix21, O_Pix22, O_Pix23 : out STD_LOGIC_VECTOR (7 downto 0);
-		   O_Pix31, O_Pix32, O_Pix33 : out STD_LOGIC_VECTOR (7 downto 0)		   
-		   ); 
+    port (I_clk                     : in  std_logic;
+          I_pixel                   : in  std_logic_vector (7 downto 0);  -- Pixel from the memory
+          I_ldPix11                 : in  std_logic;
+          I_ldPix21                 : in  std_logic;
+          I_ldPix31                 : in  std_logic;
+          I_shReg                   : in  std_logic;
+          O_Pix11, O_Pix12, O_Pix13 : out std_logic_vector (7 downto 0);
+          O_Pix21, O_Pix22, O_Pix23 : out std_logic_vector (7 downto 0);
+          O_Pix31, O_Pix32, O_Pix33 : out std_logic_vector (7 downto 0)
+          );
 end regUnit;
 
-
 architecture Behavioral of regUnit is
 
-
-signal S_Pix11, S_Pix12, S_Pix13 : STD_LOGIC_VECTOR (7 downto 0);
-signal S_Pix21, S_Pix22, S_Pix23 : STD_LOGIC_VECTOR (7 downto 0);
-signal S_Pix31, S_Pix32, S_Pix33 : STD_LOGIC_VECTOR (7 downto 0);	
+    signal S_Pix11, S_Pix12, S_Pix13 : std_logic_vector (7 downto 0) := (others => '0');
+    signal S_Pix21, S_Pix22, S_Pix23 : std_logic_vector (7 downto 0) := (others => '0');
+    signal S_Pix31, S_Pix32, S_Pix33 : std_logic_vector (7 downto 0) := (others => '0');
 
 begin
 
-	-- banc de registres
-	process(_BLANK_)
-	begin
-	if(reset = '1') then
-		S_Pix11 <= (others => '0');
-		S_Pix12 <= (others => '0');
-		S_Pix13 <= (others => '0');
-		S_Pix21 <= (others => '0');
-		S_Pix22 <= (others => '0');
-		S_Pix23 <= (others => '0');
-		S_Pix31 <= (others => '0');
-		S_Pix32 <= (others => '0');
-		S_Pix33 <= (others => '0');		
-	elsif(rising_edge(clk)) then
-	
-		_BLANK_
-		
-	end if;
-	end process;
+    -- banc de registres
+    process(I_clk)
+    begin
+        if(rising_edge(I_clk)) then
 
-	-- Connecter les sorties des registres aux ports 
-	-- d’entrée/sortie du banc de registres 
-	O_Pix11 <= S_Pix11;
-	O_Pix12 <= S_Pix12;
-	O_Pix13 <= S_Pix13;
-	O_Pix21 <= S_Pix21;
-	O_Pix22 <= S_Pix22;
-	O_Pix23 <= S_Pix23;
-	O_Pix31 <= S_Pix31;
-	O_Pix32 <= S_Pix32;
-	O_Pix33 <= S_Pix33;
-	
-end Behavioral;
+--
+-- Write here your VHDL code
+--
 
+        end if;
+    end process;
+
+    O_Pix11 <= S_Pix11;
+    O_Pix12 <= S_Pix12;
+    O_Pix13 <= S_Pix13;
+    O_Pix21 <= S_Pix21;
+    O_Pix22 <= S_Pix22;
+    O_Pix23 <= S_Pix23;
+    O_Pix31 <= S_Pix31;
+    O_Pix32 <= S_Pix32;
+    O_Pix33 <= S_Pix33;
+
+end Behavioral;