add Nexys A7 constraint file

src/Nexys4VideoA7_Sobel.xdc

+## This file is a general .xdc for the Nexys A7-100T
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+## Note: As the Nexys 4 DDR was rebranded to the Nexys A7 with no substantial changes, this XDC file will also work for the Nexys 4 DDR.
+
+## Clock signal
+set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { I_clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {I_clk}];
+
+
+##Switches
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
+#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
+#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
+#set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
+#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
+#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
+#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
+#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
+#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
+#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
+
+## LEDs
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
+#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
+#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
+#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
+#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
+
+## RGB LEDs
+#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
+#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
+#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
+
+##7 segment display
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
+#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
+#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
+#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
+#set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
+#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
+
+##CPU Reset Button
+set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { I_rst }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
+
+##Buttons
+set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { I_go }]; #IO_L9P_T1_DQS_14 Sch=btnc
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
+
+
+##Pmod Headers
+##Pmod Header JA
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
+
+##Pmod Header JB
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
+#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
+#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
+#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
+#set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
+#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
+#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
+
+##Pmod Header JD
+#set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
+#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
+#set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
+#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
+
+##Pmod Header JXADC
+#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
+#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
+#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
+#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
+#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
+
+##VGA Connector
+set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { O_vga_red[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
+set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { O_vga_red[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
+set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { O_vga_red[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
+set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { O_vga_red[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
+set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { O_vga_green[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
+set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { O_vga_green[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
+set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { O_vga_green[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
+set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { O_vga_green[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
+set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { O_vga_blue[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
+set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { O_vga_blue[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
+set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { O_vga_blue[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
+set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { O_vga_blue[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
+set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { O_vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs
+set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33 } [get_ports { O_vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
+
+##Micro SD Connector
+#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
+#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
+#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
+#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
+#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
+#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
+
+##Accelerometer
+#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
+#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
+#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
+#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
+#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
+
+##Temperature Sensor
+#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
+#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
+#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
+#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
+
+##Omnidirectional Microphone
+#set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
+#set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
+#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
+
+##PWM Audio Amplifier
+#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
+#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
+
+##USB-RS232 Interface
+#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
+#set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
+#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
+
+##USB HID (PS/2)
+#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
+#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
+
+##SMSC Ethernet PHY
+#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
+#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
+#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
+#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
+#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
+#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
+
+##Quad SPI Flash
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn

src/Nexys4_Sobel.xdc

@@ -10,100 +10,100 @@
 
 #Nexys4 User Demo User Constraint File
 # System Clock, 100MHz
-set_property PACKAGE_PIN E3 [get_ports clk_i]
+set_property PACKAGE_PIN E3 [get_ports I_clk]
 # The conversion of 'IOSTANDARD' constraint on 'net' object 'clk_i' has been applied to the port object 'clk_i'.
-set_property IOSTANDARD LVCMOS33 [get_ports clk_i]
+set_property IOSTANDARD LVCMOS33 [get_ports I_clk]
 #
 #
 #
 ##Buttons
 ##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15,		Sch name = CPU_RESET
-set_property PACKAGE_PIN C12 [get_ports reset_i]				
-	set_property IOSTANDARD LVCMOS33 [get_ports reset_i]
+set_property PACKAGE_PIN C12 [get_ports I_rst]
+set_property IOSTANDARD LVCMOS33 [get_ports I_rst]
+#
 #
-#	
 ##Bank = 15, Pin name = IO_L11N_T1_SRCC_15,	        Sch name = BTNC
-set_property PACKAGE_PIN E16 [get_ports go_i]						
-set_property IOSTANDARD LVCMOS33 [get_ports go_i]
+set_property PACKAGE_PIN E16 [get_ports I_go]
+set_property IOSTANDARD LVCMOS33 [get_ports I_go]
 #
 #
 # VGA Signals
-set_property PACKAGE_PIN A3 [get_ports {vga_red_o[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[0]' has been applied to the port object 'vga_red_o[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[0]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[0]' has been applied to the port object 'vga_red_o[0]'.
-set_property SLEW FAST [get_ports {vga_red_o[0]}]
-set_property PACKAGE_PIN B4 [get_ports {vga_red_o[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[1]' has been applied to the port object 'vga_red_o[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[1]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[1]' has been applied to the port object 'vga_red_o[1]'.
-set_property SLEW FAST [get_ports {vga_red_o[1]}]
-set_property PACKAGE_PIN C5 [get_ports {vga_red_o[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[2]' has been applied to the port object 'vga_red_o[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[2]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[2]' has been applied to the port object 'vga_red_o[2]'.
-set_property SLEW FAST [get_ports {vga_red_o[2]}]
-set_property PACKAGE_PIN A4 [get_ports {vga_red_o[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[3]' has been applied to the port object 'vga_red_o[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[3]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[3]' has been applied to the port object 'vga_red_o[3]'.
-set_property SLEW FAST [get_ports {vga_red_o[3]}]
-set_property PACKAGE_PIN B7 [get_ports {vga_blue_o[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[0]' has been applied to the port object 'vga_blue_o[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[0]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[0]' has been applied to the port object 'vga_blue_o[0]'.
-set_property SLEW FAST [get_ports {vga_blue_o[0]}]
-set_property PACKAGE_PIN C7 [get_ports {vga_blue_o[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[1]' has been applied to the port object 'vga_blue_o[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[1]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[1]' has been applied to the port object 'vga_blue_o[1]'.
-set_property SLEW FAST [get_ports {vga_blue_o[1]}]
-set_property PACKAGE_PIN D7 [get_ports {vga_blue_o[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[2]' has been applied to the port object 'vga_blue_o[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[2]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[2]' has been applied to the port object 'vga_blue_o[2]'.
-set_property SLEW FAST [get_ports {vga_blue_o[2]}]
-set_property PACKAGE_PIN D8 [get_ports {vga_blue_o[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[3]' has been applied to the port object 'vga_blue_o[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[3]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[3]' has been applied to the port object 'vga_blue_o[3]'.
-set_property SLEW FAST [get_ports {vga_blue_o[3]}]
-set_property PACKAGE_PIN C6 [get_ports {vga_green_o[0]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[0]' has been applied to the port object 'vga_green_o[0]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[0]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[0]' has been applied to the port object 'vga_green_o[0]'.
-set_property SLEW FAST [get_ports {vga_green_o[0]}]
-set_property PACKAGE_PIN A5 [get_ports {vga_green_o[1]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[1]' has been applied to the port object 'vga_green_o[1]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[1]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[1]' has been applied to the port object 'vga_green_o[1]'.
-set_property SLEW FAST [get_ports {vga_green_o[1]}]
-set_property PACKAGE_PIN B6 [get_ports {vga_green_o[2]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[2]' has been applied to the port object 'vga_green_o[2]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[2]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[2]' has been applied to the port object 'vga_green_o[2]'.
-set_property SLEW FAST [get_ports {vga_green_o[2]}]
-set_property PACKAGE_PIN A6 [get_ports {vga_green_o[3]}]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[3]' has been applied to the port object 'vga_green_o[3]'.
-set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[3]}]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[3]' has been applied to the port object 'vga_green_o[3]'.
-set_property SLEW FAST [get_ports {vga_green_o[3]}]
-set_property PACKAGE_PIN B11 [get_ports vga_hs_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_hs_o' has been applied to the port object 'vga_hs_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports vga_hs_o]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_hs_o' has been applied to the port object 'vga_hs_o'.
-set_property SLEW FAST [get_ports vga_hs_o]
-set_property PACKAGE_PIN B12 [get_ports vga_vs_o]
-# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_vs_o' has been applied to the port object 'vga_vs_o'.
-set_property IOSTANDARD LVCMOS33 [get_ports vga_vs_o]
-# The conversion of 'SLEW' constraint on 'net' object 'vga_vs_o' has been applied to the port object 'vga_vs_o'.
-set_property SLEW FAST [get_ports vga_vs_o]
+set_property PACKAGE_PIN A3 [get_ports {O_vga_red[0]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_red[0]' has been applied to the port object 'O_vga_red[0]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_red[0]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_red[0]' has been applied to the port object 'O_vga_red[0]'.
+set_property SLEW FAST [get_ports {O_vga_red[0]}]
+set_property PACKAGE_PIN B4 [get_ports {O_vga_red[1]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_red[1]' has been applied to the port object 'O_vga_red[1]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_red[1]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_red[1]' has been applied to the port object 'O_vga_red[1]'.
+set_property SLEW FAST [get_ports {O_vga_red[1]}]
+set_property PACKAGE_PIN C5 [get_ports {O_vga_red[2]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_red[2]' has been applied to the port object 'O_vga_red[2]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_red[2]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_red[2]' has been applied to the port object 'O_vga_red[2]'.
+set_property SLEW FAST [get_ports {O_vga_red[2]}]
+set_property PACKAGE_PIN A4 [get_ports {O_vga_red[3]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_red[3]' has been applied to the port object 'O_vga_red[3]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_red[3]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_red[3]' has been applied to the port object 'O_vga_red[3]'.
+set_property SLEW FAST [get_ports {O_vga_red[3]}]
+set_property PACKAGE_PIN B7 [get_ports {O_vga_blue[0]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_blue[0]' has been applied to the port object 'O_vga_blue[0]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_blue[0]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_blue[0]' has been applied to the port object 'O_vga_blue[0]'.
+set_property SLEW FAST [get_ports {O_vga_blue[0]}]
+set_property PACKAGE_PIN C7 [get_ports {O_vga_blue[1]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_blue[1]' has been applied to the port object 'O_vga_blue[1]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_blue[1]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_blue[1]' has been applied to the port object 'O_vga_blue[1]'.
+set_property SLEW FAST [get_ports {O_vga_blue[1]}]
+set_property PACKAGE_PIN D7 [get_ports {O_vga_blue[2]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_blue[2]' has been applied to the port object 'O_vga_blue[2]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_blue[2]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_blue[2]' has been applied to the port object 'O_vga_blue[2]'.
+set_property SLEW FAST [get_ports {O_vga_blue[2]}]
+set_property PACKAGE_PIN D8 [get_ports {O_vga_blue[3]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_blue[3]' has been applied to the port object 'O_vga_blue[3]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_blue[3]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_blue[3]' has been applied to the port object 'O_vga_blue[3]'.
+set_property SLEW FAST [get_ports {O_vga_blue[3]}]
+set_property PACKAGE_PIN C6 [get_ports {O_vga_green[0]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_green[0]' has been applied to the port object 'O_vga_green[0]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_green[0]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_green[0]' has been applied to the port object 'O_vga_green[0]'.
+set_property SLEW FAST [get_ports {O_vga_green[0]}]
+set_property PACKAGE_PIN A5 [get_ports {O_vga_green[1]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_green[1]' has been applied to the port object 'O_vga_green[1]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_green[1]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_green[1]' has been applied to the port object 'O_vga_green[1]'.
+set_property SLEW FAST [get_ports {O_vga_green[1]}]
+set_property PACKAGE_PIN B6 [get_ports {O_vga_green[2]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_green[2]' has been applied to the port object 'O_vga_green[2]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_green[2]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_green[2]' has been applied to the port object 'O_vga_green[2]'.
+set_property SLEW FAST [get_ports {O_vga_green[2]}]
+set_property PACKAGE_PIN A6 [get_ports {O_vga_green[3]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_green[3]' has been applied to the port object 'O_vga_green[3]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {O_vga_green[3]}]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_green[3]' has been applied to the port object 'O_vga_green[3]'.
+set_property SLEW FAST [get_ports {O_vga_green[3]}]
+set_property PACKAGE_PIN B11 [get_ports O_vga_hs]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_hs' has been applied to the port object 'O_vga_hs'.
+set_property IOSTANDARD LVCMOS33 [get_ports O_vga_hs]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_hs' has been applied to the port object 'O_vga_hs'.
+set_property SLEW FAST [get_ports O_vga_hs]
+set_property PACKAGE_PIN B12 [get_ports O_vga_vs]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'O_vga_vs' has been applied to the port object 'O_vga_vs'.
+set_property IOSTANDARD LVCMOS33 [get_ports O_vga_vs]
+# The conversion of 'SLEW' constraint on 'net' object 'O_vga_vs' has been applied to the port object 'O_vga_vs'.
+set_property SLEW FAST [get_ports O_vga_vs]
 
 # Incoming System Clock PERIOD Constraint
 
 # All timing constraint translations are rough conversions, intended to act as a template for further manual refinement. The translations should not be expected to produce semantically identical results to the original ucf. Each xdc timing constraint must be manually inspected and verified to ensure it captures the desired intent
 
-create_clock -name clk_i -period 10.000 [get_ports clk_i]
+create_clock -name I_clk -period 10.000 [get_ports I_clk]
 
 # Ignore Clock Domain Crossing signals
 # These signals are coming from the 100MHz clock domain
@@ -112,4 +112,4 @@ create_clock -name clk_i -period 10.000 [get_ports clk_i]
 
 # Define a new TNM for a FROM - TO constraint
 
-#get_false_path -from [all_fanout -endpoints_only -only_cells -flat -from [get_nets clk_i]] -to [all_fanout -endpoints_only -flat -from [get_nets Inst_VGA/pxl_clk]]
+#get_false_path -from [all_fanout -endpoints_only -only_cells -flat -from [get_nets I_clk]] -to [all_fanout -endpoints_only -flat -from [get_nets Inst_VGA/pxl_clk]]

src/operativeUnit.vhd

 
 library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
 
 
-entity  operativeUnit is
-    Port ( clk		:in STD_LOGIC;
-		   reset	:in STD_LOGIC;
-		   I_pixel : in  STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
-           I_ldPix11 : in  STD_LOGIC;
-           I_ldPix21 : in  STD_LOGIC;
-           I_ldPix31 : in  STD_LOGIC;
-           I_shReg : in  STD_LOGIC;
-		   I_ldPixEdge : in STD_LOGIC;
-		   O_pixEdge : out  STD_LOGIC		   
-		   ); 
-end  operativeUnit;
+entity operativeUnit is
+    port (
+        I_clk       : in  std_logic;
+        I_pixel     : in  std_logic_vector (7 downto 0);  -- Pixel from the memory
+        I_ldPix11   : in  std_logic;
+        I_ldPix21   : in  std_logic;
+        I_ldPix31   : in  std_logic;
+        I_shReg     : in  std_logic;
+        I_ldPixEdge : in  std_logic;
+        O_pixEdge   : out std_logic
+        );
+end operativeUnit;
 
 
-architecture Behavioral of  operativeUnit is
+architecture Behavioral of operativeUnit is
 
 -- déclaration des sous-composants
 
-  -- banc de registres
-  component regUnit is
-    port (clk,reset	:in STD_LOGIC;
-		   I_pixel : in  STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
-           I_ldPix11 : in  STD_LOGIC;
-           I_ldPix21 : in  STD_LOGIC;
-           I_ldPix31 : in  STD_LOGIC;
-           I_shReg : in  STD_LOGIC;
-		   O_Pix11, O_Pix12, O_Pix13 : out STD_LOGIC_VECTOR (7 downto 0);
-		   O_Pix21, O_Pix22, O_Pix23 : out STD_LOGIC_VECTOR (7 downto 0);
-		   O_Pix31, O_Pix32, O_Pix33 : out STD_LOGIC_VECTOR (7 downto 0)	
-		   );
-  end component regUnit;
-  
-  -- unité de calcul du gradient
-  component gradientUnit is
-    port ( I_Pix11, I_Pix12, I_Pix13 : in STD_LOGIC_VECTOR (7 downto 0);
-		   I_Pix21, I_Pix22, I_Pix23 : in STD_LOGIC_VECTOR (7 downto 0);
-		   I_Pix31, I_Pix32, I_Pix33 : in STD_LOGIC_VECTOR (7 downto 0);
-		   O_pixEdge : out  STD_LOGIC		
-		   );
-  end component gradientUnit;
-  
-  -- registre de sortie
-  component pixedgeReg is
-    Port (clk,reset	:in STD_LOGIC;
-		   I_pixEdge : in  STD_LOGIC;
-		   I_ldPixEdge : in STD_LOGIC;
-		   O_pixEdge : out  STD_LOGIC		   
-		   ); 
-  end component pixedgeReg;
- 
+    -- banc de registres
+    component regUnit is
+        port (I_clk                     : in  std_logic;
+              I_pixel                   : in  std_logic_vector (7 downto 0);  -- Pixel from the memory
+              I_ldPix11                 : in  std_logic;
+              I_ldPix21                 : in  std_logic;
+              I_ldPix31                 : in  std_logic;
+              I_shReg                   : in  std_logic;
+              O_Pix11, O_Pix12, O_Pix13 : out std_logic_vector (7 downto 0);
+              O_Pix21, O_Pix22, O_Pix23 : out std_logic_vector (7 downto 0);
+              O_Pix31, O_Pix32, O_Pix33 : out std_logic_vector (7 downto 0)
+              );
+    end component regUnit;
+
+    -- unité de calcul du gradient
+    component gradientUnit is
+        port (I_Pix11, I_Pix12, I_Pix13 : in  std_logic_vector (7 downto 0);
+              I_Pix21, I_Pix22, I_Pix23 : in  std_logic_vector (7 downto 0);
+              I_Pix31, I_Pix32, I_Pix33 : in  std_logic_vector (7 downto 0);
+              O_pixEdge                 : out std_logic
+              );
+    end component gradientUnit;
+
+    -- registre de sortie
+    component pixedgeReg is
+        port (I_clk : in  std_logic;
+              I_pixEdge    : in  std_logic;
+              I_ldPixEdge  : in  std_logic;
+              O_pixEdge    : out std_logic
+              );
+    end component pixedgeReg;
+
 -- déclaration des signaux internes
-signal S_Pix11, S_Pix12, S_Pix13 : STD_LOGIC_VECTOR (7 downto 0);
-signal S_Pix21, S_Pix22, S_Pix23 : STD_LOGIC_VECTOR (7 downto 0);
-signal S_Pix31, S_Pix32, S_Pix33 : STD_LOGIC_VECTOR (7 downto 0);	
-signal S_pixEdge : STD_LOGIC;
+    signal S_Pix11, S_Pix12, S_Pix13 : std_logic_vector (7 downto 0);
+    signal S_Pix21, S_Pix22, S_Pix23 : std_logic_vector (7 downto 0);
+    signal S_Pix31, S_Pix32, S_Pix33 : std_logic_vector (7 downto 0);
+    signal S_pixEdge                 : std_logic;
 
 begin
 
 -- instanciation des sous-composants et établissement des interconnexions
-  
-  -- instanciation d'un banc de registres
-  regUnit_1 : entity work.regUnit
-    port map (
-      clk          => clk,
-      reset        => reset,
-      I_pixel      => I_pixel,   
-      I_ldPix11    => I_ldPix11,
-      I_ldPix21    => I_ldPix21,
-      I_ldPix31    => I_ldPix31,
-      I_shReg      => I_shReg,
-      O_Pix11      => S_Pix11,
-      O_Pix12      => S_Pix12,
-      O_Pix13      => S_Pix13,
-      O_Pix21      => S_Pix21,
-      O_Pix22      => S_Pix22,
-      O_Pix23      => S_Pix23,
-      O_Pix31      => S_Pix31,
-      O_Pix32      => S_Pix32,
-      O_Pix33      => S_Pix33);
-	  
-  -- instanciation d'une unité de calcul du gradient 
-  gradientUnit_1 : entity work.gradientUnit
-    port map (
-      O_pixEdge    => S_pixEdge,
-      I_Pix11      => S_Pix11,
-      I_Pix12      => S_Pix12,
-      I_Pix13      => S_Pix13,
-      I_Pix21      => S_Pix21,
-      I_Pix22      => S_Pix22,
-      I_Pix23      => S_Pix23,
-      I_Pix31      => S_Pix31,
-      I_Pix32      => S_Pix32,
-      I_Pix33      => S_Pix33);
-	  
-  -- instanciation d'un registre de sortie
-  pixedgeReg_1 : entity work.pixedgeReg
-    port map (
-      clk          => clk,
-      reset        => reset,
-	  I_pixEdge    => S_pixEdge,
-      I_ldPixEdge  => I_ldPixEdge,
-      O_pixEdge    => O_pixEdge);
-  
-end Behavioral;
 
+    -- instanciation d'un banc de registres
+    regUnit_1 : entity work.regUnit
+        port map (
+            I_clk     => I_clk,
+            I_pixel   => I_pixel,
+            I_ldPix11 => I_ldPix11,
+            I_ldPix21 => I_ldPix21,
+            I_ldPix31 => I_ldPix31,
+            I_shReg   => I_shReg,
+            O_Pix11   => S_Pix11,
+            O_Pix12   => S_Pix12,
+            O_Pix13   => S_Pix13,
+            O_Pix21   => S_Pix21,
+            O_Pix22   => S_Pix22,
+            O_Pix23   => S_Pix23,
+            O_Pix31   => S_Pix31,
+            O_Pix32   => S_Pix32,
+            O_Pix33   => S_Pix33);
+
+    -- instanciation d'une unité de calcul du gradient
+    gradientUnit_1 : entity work.gradientUnit
+        port map (
+            O_pixEdge => S_pixEdge,
+            I_Pix11   => S_Pix11,
+            I_Pix12   => S_Pix12,
+            I_Pix13   => S_Pix13,
+            I_Pix21   => S_Pix21,
+            I_Pix22   => S_Pix22,
+            I_Pix23   => S_Pix23,
+            I_Pix31   => S_Pix31,
+            I_Pix32   => S_Pix32,
+            I_Pix33   => S_Pix33);
+
+    -- instanciation d'un registre de sortie
+    pixedgeReg_1 : entity work.pixedgeReg
+        port map (
+            I_clk       => I_clk,
+            I_pixEdge   => S_pixEdge,
+            I_ldPixEdge => I_ldPixEdge,
+            O_pixEdge   => O_pixEdge);
+
+end Behavioral;