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README.md

+# Sobel VHDL Lab
+
+- The questions must be answerd in the `docs/report.md` markdown document.
+- The FSM diagram and the address generator architecture must be updated in the `docs/img/soble-FSM.drawio` and `docs/img/sobel-adrgenUnit.drawio` with the [Draw.io tool](https://app.diagrams.net/){:target="_blank"}

docs/report.md

+# Soble Lab Report
+
+Name:
+Name:
+
+## Question 1: What is the nature of the VHDL process that describes the register bank? Its sensitivity list? Did the functional simulation validate the module? Justify
+
+
+## Question 2: Give the results obtained
+
+
+## Question 3: What type and quantification did you use for the internal signals? Justify.
+
+
+## Question 4: How many processes are used and what are their natures? Sensitivity list? Did the functional simulation validate the module? Justify
+
+
+## Question 5: Give the results obtained
+
+
+## Question 6: Did the functional simulation validate the module? Justify
+
+
+## Question 7: Give and comment on the results obtained
+
+
+## Question 8: Give the architecture you propose for the address generator
+
+
+## Question 9: Did the functional simulation validate the module? Justify
+
+
+## Question 10: Give the results obtained
+
+
+## Question 11: Complete the state machine diagram
+
+
+!!! info
+    This diagram is to be completed in order to then complete the VHDL file `automate.vhd`. To do this, you can use the file `automate.drawio` available in the git repository, it is the file `docs/img/automate.drawio` with the tool [https://app.diagrams.net/](https://app.diagrams.net/). Then update the file `automate.png` by exporting the diagram `automate.drawio` previously updated.
+
+![FSM diagram](./img/sobel-FSM.png)
+
+
+## Question 12: How many processes are used to describe the FSM, and what are their natures? Their sensitivity lists? Did the functional simulation validate the module? Justify
+
+
+## Question 13: Give the results obtained
+
+
+## Question 14: Did the functional simulation validate the module? Justify
+
+
+## Question 15: Give and comment on the results obtained. What is the percentage of resources used by the Sobel processor compared to those available on the target Artix 7 FPGA `XC7A100T-CSG324-1`. Comment
+
+
+## Question 16: Give and comment on the results obtained.
+
+
+## Question 17: Is the prototyping and demonstration on the board conclusive?
+
+
+## Question 18: Identify the maximum clock frequency achievable on this FPGA
+
+
+## Question 19: How many clock cycles are needed to process a pixel?
+
+
+## Question 20: How many clock cycles are needed to process a 396x396 definition image
+
+
+## Question 21: How many 396x396 definition images can this processor process per second?

docs/report.md~

+#

src/DualPortRamGeneric.vhd

+--
+-- Dual-Port RAM with Enable on Each Port
+-- 1st port implements read and write
+-- 2nd port only read
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity DualPortRamGeneric is
+    generic(
+        G_MemoryWidth   : integer;  
+        G_MemoryDepth   : integer;  
+        G_AddressWidth  : integer   
+    );
+	port (	
+		I_clk   : in std_logic;
+		I_ena   : in std_logic;
+		I_enb   : in std_logic;
+		I_wea   : in std_logic;
+		I_addra : in std_logic_vector(G_AddressWidth-1 downto 0);
+		I_addrb : in std_logic_vector(G_AddressWidth-1 downto 0);
+		I_dina   : in std_logic_vector(G_MemoryWidth-1 downto 0);
+		O_douta   : out std_logic_vector(G_MemoryWidth-1 downto 0);
+		O_doutb   : out std_logic_vector(G_MemoryWidth-1 downto 0)
+	);
+end DualPortRamGeneric;
+
+architecture rtl of DualPortRamGeneric is
+
+	type ram_type is array (0 to G_MemoryDepth-1) of std_logic_vector(G_MemoryWidth-1 downto 0);
+	signal RAM : ram_type := (others => (others => '1')); -- attention initialisation  '1'
+	signal read_addra : std_logic_vector(G_AddressWidth-1 downto 0);
+	signal read_addrb : std_logic_vector(G_AddressWidth-1 downto 0);
+
+begin
+
+-- pragma synthesis_off
+	assert (not( G_MemoryDepth > 2**G_AddressWidth)) 
+	report "bad value for G_MemoryDepth or G_AddressWidth" 
+	severity error;
+-- pragma synthesis_on
+
+
+  process (I_clk)
+  begin
+  	if (I_clk'event and I_clk = '1') then
+  		if (I_ena = '1') then
+  			if (I_wea = '1') then
+  				RAM(to_integer(unsigned(I_addra))) <= I_dina;
+  			end if;
+  			read_addra <= I_addra;
+  		end if;
+  		if (I_enb = '1') then
+  			read_addrb <= I_addrb;
+  		end if;
+  	end if;
+  end process;
+  
+  O_douta <= RAM(to_integer(unsigned(read_addra)));
+  O_doutb <= RAM(to_integer(unsigned(read_addrb)));
+
+end rtl;
+
+-- The following is an instantiation template
+--
+--
+-- Component Declaration
+--component DualPortRamGeneric is
+-- generic (
+--          G_MemoryWidth  : Integer;
+--          G_MemoryDepth  : Integer;
+--          G_AddressWidth : Integer
+--          );
+--port (
+--		I_clk   : in std_logic;
+--		I_ena   : in std_logic;
+--		I_enb   : in std_logic;
+--		I_wea   : in std_logic;
+--		I_addra : in std_logic_vector(G_AddressWidth-1 downto 0);
+--		I_addrb : in std_logic_vector(G_AddressWidth-1 downto 0);
+--		I_dina   : in std_logic_vector(G_MemoryWidth-1 downto 0);
+--		O_douta   : out std_logic_vector(G_MemoryWidth-1 downto 0);
+--		O_doutb   : out std_logic_vector(G_MemoryWidth-1 downto 0)
+--      );
+--end component;
+
+-- Instantiation
+--<your_instance_name> : DualPortRamGeneric
+-- generic map (
+--      G_MemoryWidth => 8,
+--      G_MemoryDepth => 10000,
+--      G_AddressWidth => 14
+--      )
+-- port map (
+--      I_clk    => clk,
+--      I_ena    => ena,  
+--      I_enb    => enb,  
+--      I_wea    => wea,  
+--      I_addra  => addra,
+--      I_addrb  => addrb,
+--      I_dina   => dina, 
+--      O_douta  => douta,
+--      O_doutb  => doutb
+--      );
+
+
+
+
+

src/Nexys4_Sobel.xdc

+
+####################################################################################
+# Generated by PlanAhead 14.7 built on 'Fri Sep 27 19:29:51 MDT 2013' by 'xbuild'
+####################################################################################
+
+
+####################################################################################
+# Constraints from file : 'Nexys4UserDemo.ucf'
+####################################################################################
+
+#Nexys4 User Demo User Constraint File
+# System Clock, 100MHz
+set_property PACKAGE_PIN E3 [get_ports clk_i]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'clk_i' has been applied to the port object 'clk_i'.
+set_property IOSTANDARD LVCMOS33 [get_ports clk_i]
+#
+#
+#
+##Buttons
+##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15,		Sch name = CPU_RESET
+set_property PACKAGE_PIN C12 [get_ports reset_i]				
+	set_property IOSTANDARD LVCMOS33 [get_ports reset_i]
+#
+#	
+##Bank = 15, Pin name = IO_L11N_T1_SRCC_15,	        Sch name = BTNC
+set_property PACKAGE_PIN E16 [get_ports go_i]						
+set_property IOSTANDARD LVCMOS33 [get_ports go_i]
+#
+#
+# VGA Signals
+set_property PACKAGE_PIN A3 [get_ports {vga_red_o[0]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[0]' has been applied to the port object 'vga_red_o[0]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[0]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[0]' has been applied to the port object 'vga_red_o[0]'.
+set_property SLEW FAST [get_ports {vga_red_o[0]}]
+set_property PACKAGE_PIN B4 [get_ports {vga_red_o[1]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[1]' has been applied to the port object 'vga_red_o[1]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[1]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[1]' has been applied to the port object 'vga_red_o[1]'.
+set_property SLEW FAST [get_ports {vga_red_o[1]}]
+set_property PACKAGE_PIN C5 [get_ports {vga_red_o[2]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[2]' has been applied to the port object 'vga_red_o[2]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[2]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[2]' has been applied to the port object 'vga_red_o[2]'.
+set_property SLEW FAST [get_ports {vga_red_o[2]}]
+set_property PACKAGE_PIN A4 [get_ports {vga_red_o[3]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_red_o[3]' has been applied to the port object 'vga_red_o[3]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_red_o[3]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_red_o[3]' has been applied to the port object 'vga_red_o[3]'.
+set_property SLEW FAST [get_ports {vga_red_o[3]}]
+set_property PACKAGE_PIN B7 [get_ports {vga_blue_o[0]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[0]' has been applied to the port object 'vga_blue_o[0]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[0]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[0]' has been applied to the port object 'vga_blue_o[0]'.
+set_property SLEW FAST [get_ports {vga_blue_o[0]}]
+set_property PACKAGE_PIN C7 [get_ports {vga_blue_o[1]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[1]' has been applied to the port object 'vga_blue_o[1]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[1]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[1]' has been applied to the port object 'vga_blue_o[1]'.
+set_property SLEW FAST [get_ports {vga_blue_o[1]}]
+set_property PACKAGE_PIN D7 [get_ports {vga_blue_o[2]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[2]' has been applied to the port object 'vga_blue_o[2]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[2]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[2]' has been applied to the port object 'vga_blue_o[2]'.
+set_property SLEW FAST [get_ports {vga_blue_o[2]}]
+set_property PACKAGE_PIN D8 [get_ports {vga_blue_o[3]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_blue_o[3]' has been applied to the port object 'vga_blue_o[3]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_blue_o[3]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_blue_o[3]' has been applied to the port object 'vga_blue_o[3]'.
+set_property SLEW FAST [get_ports {vga_blue_o[3]}]
+set_property PACKAGE_PIN C6 [get_ports {vga_green_o[0]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[0]' has been applied to the port object 'vga_green_o[0]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[0]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[0]' has been applied to the port object 'vga_green_o[0]'.
+set_property SLEW FAST [get_ports {vga_green_o[0]}]
+set_property PACKAGE_PIN A5 [get_ports {vga_green_o[1]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[1]' has been applied to the port object 'vga_green_o[1]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[1]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[1]' has been applied to the port object 'vga_green_o[1]'.
+set_property SLEW FAST [get_ports {vga_green_o[1]}]
+set_property PACKAGE_PIN B6 [get_ports {vga_green_o[2]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[2]' has been applied to the port object 'vga_green_o[2]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[2]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[2]' has been applied to the port object 'vga_green_o[2]'.
+set_property SLEW FAST [get_ports {vga_green_o[2]}]
+set_property PACKAGE_PIN A6 [get_ports {vga_green_o[3]}]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_green_o[3]' has been applied to the port object 'vga_green_o[3]'.
+set_property IOSTANDARD LVCMOS33 [get_ports {vga_green_o[3]}]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_green_o[3]' has been applied to the port object 'vga_green_o[3]'.
+set_property SLEW FAST [get_ports {vga_green_o[3]}]
+set_property PACKAGE_PIN B11 [get_ports vga_hs_o]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_hs_o' has been applied to the port object 'vga_hs_o'.
+set_property IOSTANDARD LVCMOS33 [get_ports vga_hs_o]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_hs_o' has been applied to the port object 'vga_hs_o'.
+set_property SLEW FAST [get_ports vga_hs_o]
+set_property PACKAGE_PIN B12 [get_ports vga_vs_o]
+# The conversion of 'IOSTANDARD' constraint on 'net' object 'vga_vs_o' has been applied to the port object 'vga_vs_o'.
+set_property IOSTANDARD LVCMOS33 [get_ports vga_vs_o]
+# The conversion of 'SLEW' constraint on 'net' object 'vga_vs_o' has been applied to the port object 'vga_vs_o'.
+set_property SLEW FAST [get_ports vga_vs_o]
+
+# Incoming System Clock PERIOD Constraint
+
+# All timing constraint translations are rough conversions, intended to act as a template for further manual refinement. The translations should not be expected to produce semantically identical results to the original ucf. Each xdc timing constraint must be manually inspected and verified to ensure it captures the desired intent
+
+create_clock -name clk_i -period 10.000 [get_ports clk_i]
+
+# Ignore Clock Domain Crossing signals
+# These signals are coming from the 100MHz clock domain
+# ant are not time-critical: RGB LED, Temperature, Accelerometer
+# and Mouse Controller data, going to the 108Mhz clock domain, the VGA display controller
+
+# Define a new TNM for a FROM - TO constraint
+
+#get_false_path -from [all_fanout -endpoints_only -only_cells -flat -from [get_nets clk_i]] -to [all_fanout -endpoints_only -flat -from [get_nets Inst_VGA/pxl_clk]]

src/SinglePortROMFileInitGeneric.vhd

+-------------------------------------------------------------------------------
+-- Generic Single Port ROM initialized with a specified file 
+--
+
+Library ieee;
+Use ieee.std_logic_1164.All;
+Use ieee.numeric_std.All;
+Use std.textio.All;
+
+Entity SinglePortROMFileInitGeneric Is
+	Generic (
+		G_MemoryWidth  : Integer;  
+		G_MemoryDepth  : Integer;  
+		G_AddressWidth : Integer;  
+		G_InitFileName : String    
+	);
+	Port (
+		I_clk : In std_logic;
+		I_en    : In std_logic;
+		I_addr  : In std_logic_vector(G_AddressWidth - 1 Downto 0);
+		O_dout  : Out std_logic_vector(G_MemoryWidth - 1 Downto 0)
+	);
+End SinglePortROMFileInitGeneric;
+
+Architecture rtl Of SinglePortROMFileInitGeneric Is
+
+type ramtype is array (G_MemoryDepth-1 downto 0) of std_logic_vector (G_MemoryWidth-1 downto 0);          -- 2D Array Declaration for RAM signal
+
+
+impure function initramfromfile (ramfilename : in string) return ramtype is
+file ramfile	: text is in ramfilename;
+variable ramfileline : line;
+variable ram_name	: ramtype;
+variable bitvec : bit_vector(G_MemoryWidth-1 downto 0);
+begin
+    for i in ramtype'range loop
+        readline (ramfile, ramfileline);
+		exit when endfile (ramfile);
+        read (ramfileline, bitvec);
+        ram_name(i) := to_stdlogicvector(bitvec);
+    end loop;
+    return ram_name;
+end function;
+
+Signal RAM : RamType := InitRamFromFile(G_InitFileName);
+
+Begin
+-- pragma synthesis_off
+	assert (not( G_MemoryDepth > 2**G_AddressWidth)) 
+	report "bad value for G_MemoryDepth or G_AddressWidth" 
+	severity error;
+-- pragma synthesis_on
+
+	Process (I_clk)
+	Begin
+		If I_clk'EVENT and I_clk = '1' Then
+			If I_en = '1' Then
+				O_dout <= RAM(to_integer(unsigned(I_addr))); ---- uncomment to implement on BLOCK RAM
+			End If; 
+		End If;
+	End Process;
+ 
+	-- O_dout <= RAM(to_integer(unsigned(I_addr))); ---- uncomment to implement on LUT
+End rtl;
+
+
+-- The following is an instantiation template
+--
+--
+-- Component Declaration
+--component SinglePortROMFileInitGeneric is
+-- generic (
+--          G_MemoryWidth  : Integer;
+--          G_MemoryDepth  : Integer;
+--          G_AddressWidth : Integer;
+--          G_InitFileName : String  
+--          );
+--port (
+--	    I_clk : In std_logic;
+--		I_en    : In std_logic;
+--		I_addr  : In std_logic_vector(G_AddressWidth - 1 Downto 0);
+--		O_dout  : Out std_logic_vector(G_MemoryWidth - 1 Downto 0)
+--      );
+--end component;
+
+-- Instantiation
+--<your_instance_name> : SinglePortROMFileInitGeneric
+-- generic map (
+--      G_MemoryWidth => 8,
+--      G_MemoryDepth => 10000,
+--      G_AddressWidth => 14,
+--      G_InitFileName => "SobelMemIn.txt" 
+--      )
+-- port map (
+--      I_clk  => clk,
+--      I_en     => en,
+--      I_addr   => addr,
+--      O_dout   => dout
+--      );

src/adrgenUnit.vhd

+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity adrgenUnit is
+    Port ( clk	 		 : in STD_LOGIC;
+		   reset	 	 : in STD_LOGIC;
+		   I_clr_PtrLine : in STD_LOGIC;
+		   I_inc_PtrLine : in STD_LOGIC;
+		   I_clr_PtrCol  : in STD_LOGIC;
+		   I_inc_PtrCol  : in STD_LOGIC;
+		   I_selPix 	 : in STD_LOGIC_VECTOR (1 downto 0);
+		   O_EndImage	 : out STD_LOGIC;
+		   O_NewLine	 : out STD_LOGIC;
+		   O_ADR_R		 : out STD_LOGIC_VECTOR (13 downto 0); -- La profondeur de la mémoire IN = 100x100 = 10000
+		   O_ADR_W	 	 : out STD_LOGIC_VECTOR (13 downto 0)  -- La profondeur de la mémoire OUT = 100x100 = 10000   
+		   ); 
+end adrgenUnit;
+
+
+architecture Behavioral of adrgenUnit is
+
+-- déclaration des signaux internes
+	_BLANK_
+
+begin
+
+	
+	_BLANK_
+		
+
+end Behavioral;
+

src/automate.vhd

+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-----------------------------------------------------
+entity automate is
+    Port ( clk			 : in STD_LOGIC;
+		   reset		 : in STD_LOGIC;
+		   I_go	   		 : in STD_LOGIC;
+		   I_EndImage	 : in STD_LOGIC;
+		   I_NewLine	 : in STD_LOGIC;
+		   -- signaux de commandes vers l'unit oprative
+           O_ldPix11 	 : out  STD_LOGIC;
+           O_ldPix21 	 : out  STD_LOGIC;
+           O_ldPix31 	 : out  STD_LOGIC;
+           O_shReg 		 : out  STD_LOGIC;
+		   O_ldPixEdge 	 : out STD_LOGIC;
+		   -- signaux de commandes vers le gnrateur d'adresses		   
+		   O_clr_PtrLine : out STD_LOGIC;
+		   O_inc_PtrLine : out STD_LOGIC;
+		   O_clr_PtrCol  : out STD_LOGIC;
+		   O_inc_PtrCol  : out STD_LOGIC;
+		   O_selPix 	 : out STD_LOGIC_VECTOR (1 downto 0);		   
+		   -- signaux de commandes vers les mmoires		   
+		   O_enM_R		 : out STD_LOGIC;
+		   O_enM_W		 : out STD_LOGIC;
+		   -- signal de commande vers le contrleur VGA		   		   
+		   O_StartDisplay  : out STD_LOGIC		   
+		   ); 
+end automate;
+-----------------------------------------------------
+
+
+architecture Behavioral of automate is
+
+-- dfinir un type numr avec les tats de la FSM et deux signaux de ce type
+type automate_state_type is (Idle, Init, Pix1, Pix2, Pix3, sh1, Pix4, Pix5, 
+							 Pix6, sh2, Pix7, Pix8, Pix9, Exec, OutEdge, 
+							 sh3, EndSobel);
+signal current_state, next_state : automate_state_type := Idle;
+  
+begin
+
+-- Le registre d'tat
+state_reg: process(_BLANK_TO_FILL_)
+begin
+	if (reset='1') then  				-- asynchronous reset (active high)
+        current_state <= Idle;
+	elsif (clk'event and clk='1') then	-- rising edge of clk
+	    current_state <= next_state;
+	end if;
+end process state_reg;
+
+	
+-- Calcul de l'tat suivant et des sorties
+comb_logic: process(_BLANK_TO_FILL_)
+begin
+	-- initialisation de TOUTES les sorties
+    O_ldPix11		<= '0';
+    O_ldPix21 	    <= '0';
+    O_ldPix31 	    <= '0';
+    O_shReg 		<= '0'; 
+	O_ldPixEdge 	<= '0'; 
+	O_clr_PtrLine   <= '0';
+	O_inc_PtrLine   <= '0';
+	O_clr_PtrCol    <= '0';
+	O_inc_PtrCol    <= '0';
+	O_selPix 	 	<= "00";   
+	O_enM_R		    <= '0';
+	O_enM_W		    <= '0';
+	O_StartDisplay	<= '0';
+	next_state		<= Idle;
+	
+	case current_state is
+
+		when Idle =>			
+				-- calcul des sorties SPECIFIQUES  l'tat
+				O_clr_PtrLine	<= I_go;
+				O_clr_PtrCol	<= I_go;
+				
+				-- calcul de l'tat suivant
+				if(I_go = '1') then
+					next_state	<= Init;
+				else
+					next_state	<= Idle;
+				end if;
+
+		when Init =>			
+				-- calcul des sorties SPECIFIQUES  l'tat
+				O_enM_R		<= '1';
+				O_selPix	<= "00";
+				
+				-- calcul de l'tat suivant
+				next_state	<= Pix1;
+
+		when Pix1 =>			
+				-- calcul des sorties SPECIFIQUES  l'tat
+				O_ldPix11	<= '1';
+				O_enM_R		<= '1';
+				O_selPix	<= "01";
+				
+				-- calcul de l'tat suivant
+				if(I_EndImage = '0') then
+					next_state	<= Pix2;
+				else
+					next_state	<= EndSobel;
+				end if;
+				
+		when Pix2 => 
+				-- calcul des sorties SPECIFIQUES  l'tat
+				__BLANK_TO_FILL__
+				
+				-- calcul de l'tat suivant
+				next_state	<= __BLANK_TO_FILL__	
+		
+
+		
+		
+
+		
+		
+		__BLANK_TO_FILL__
+			
+
+
+
+			
+			
+	    when others =>	
+				next_state	<= Idle;
+	end case;
+end process comb_logic;
+	
+end Behavioral;
+
+
+

src/gradientUnit.vhd

+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity gradientUnit is
+    Port ( I_Pix11, I_Pix12, I_Pix13 : in STD_LOGIC_VECTOR (7 downto 0);
+		   I_Pix21, I_Pix22, I_Pix23 : in STD_LOGIC_VECTOR (7 downto 0);
+		   I_Pix31, I_Pix32, I_Pix33 : in STD_LOGIC_VECTOR (7 downto 0);
+		   O_pixEdge : out  STD_LOGIC		   
+		   ); 
+end gradientUnit;
+
+
+architecture Behavioral of gradientUnit is
+
+-- déclaration des signaux internes
+	_BLANK_
+
+begin
+
+	
+	_BLANK_
+		
+
+end Behavioral;
+

src/ip/clk_wiz_vga_25MHz/clk_wiz_vga_25MHz.vho

+
+-- (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+--  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+--   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+------------------------------------------------------------------------------
+-- clk_out1__25.00000______0.000______50.0______181.828____104.359
+--
+------------------------------------------------------------------------------
+-- Input Clock   Freq (MHz)    Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_vga_25MHz
+port
+ (-- Clock in ports
+  -- Clock out ports
+  clk_out1          : out    std_logic;
+  -- Status and control signals
+  locked            : out    std_logic;
+  clk_in1           : in     std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_vga_25MHz
+   port map ( 
+  -- Clock out ports  
+   clk_out1 => clk_out1,
+  -- Status and control signals                
+   locked => locked,
+   -- Clock in ports
+   clk_in1 => clk_in1
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------

src/operativeUnit.vhd

+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity  operativeUnit is
+    Port ( clk		:in STD_LOGIC;
+		   reset	:in STD_LOGIC;
+		   I_pixel : in  STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
+           I_ldPix11 : in  STD_LOGIC;
+           I_ldPix21 : in  STD_LOGIC;
+           I_ldPix31 : in  STD_LOGIC;
+           I_shReg : in  STD_LOGIC;
+		   I_ldPixEdge : in STD_LOGIC;
+		   O_pixEdge : out  STD_LOGIC		   
+		   ); 
+end  operativeUnit;
+
+
+architecture Behavioral of  operativeUnit is
+
+-- déclaration des sous-composants
+
+  -- banc de registres
+  component regUnit is
+    port (clk,reset	:in STD_LOGIC;
+		   I_pixel : in  STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
+           I_ldPix11 : in  STD_LOGIC;
+           I_ldPix21 : in  STD_LOGIC;
+           I_ldPix31 : in  STD_LOGIC;
+           I_shReg : in  STD_LOGIC;
+		   O_Pix11, O_Pix12, O_Pix13 : out STD_LOGIC_VECTOR (7 downto 0);
+		   O_Pix21, O_Pix22, O_Pix23 : out STD_LOGIC_VECTOR (7 downto 0);
+		   O_Pix31, O_Pix32, O_Pix33 : out STD_LOGIC_VECTOR (7 downto 0)	
+		   );
+  end component regUnit;
+  
+  -- unité de calcul du gradient
+  component gradientUnit is
+    port ( I_Pix11, I_Pix12, I_Pix13 : in STD_LOGIC_VECTOR (7 downto 0);
+		   I_Pix21, I_Pix22, I_Pix23 : in STD_LOGIC_VECTOR (7 downto 0);
+		   I_Pix31, I_Pix32, I_Pix33 : in STD_LOGIC_VECTOR (7 downto 0);
+		   O_pixEdge : out  STD_LOGIC		
+		   );
+  end component gradientUnit;
+  
+  -- registre de sortie
+  component pixedgeReg is
+    Port (clk,reset	:in STD_LOGIC;
+		   I_pixEdge : in  STD_LOGIC;
+		   I_ldPixEdge : in STD_LOGIC;
+		   O_pixEdge : out  STD_LOGIC		   
+		   ); 
+  end component pixedgeReg;
+ 
+-- déclaration des signaux internes
+signal S_Pix11, S_Pix12, S_Pix13 : STD_LOGIC_VECTOR (7 downto 0);
+signal S_Pix21, S_Pix22, S_Pix23 : STD_LOGIC_VECTOR (7 downto 0);
+signal S_Pix31, S_Pix32, S_Pix33 : STD_LOGIC_VECTOR (7 downto 0);	
+signal S_pixEdge : STD_LOGIC;
+
+begin
+
+-- instanciation des sous-composants et établissement des interconnexions
+  
+  -- instanciation d'un banc de registres
+  regUnit_1 : entity work.regUnit
+    port map (
+      clk          => clk,
+      reset        => reset,
+      I_pixel      => I_pixel,   
+      I_ldPix11    => I_ldPix11,
+      I_ldPix21    => I_ldPix21,
+      I_ldPix31    => I_ldPix31,
+      I_shReg      => I_shReg,
+      O_Pix11      => S_Pix11,
+      O_Pix12      => S_Pix12,
+      O_Pix13      => S_Pix13,
+      O_Pix21      => S_Pix21,
+      O_Pix22      => S_Pix22,
+      O_Pix23      => S_Pix23,
+      O_Pix31      => S_Pix31,
+      O_Pix32      => S_Pix32,
+      O_Pix33      => S_Pix33);
+	  
+  -- instanciation d'une unité de calcul du gradient 
+  gradientUnit_1 : entity work.gradientUnit
+    port map (
+      O_pixEdge    => S_pixEdge,
+      I_Pix11      => S_Pix11,
+      I_Pix12      => S_Pix12,
+      I_Pix13      => S_Pix13,
+      I_Pix21      => S_Pix21,
+      I_Pix22      => S_Pix22,
+      I_Pix23      => S_Pix23,
+      I_Pix31      => S_Pix31,
+      I_Pix32      => S_Pix32,
+      I_Pix33      => S_Pix33);
+	  
+  -- instanciation d'un registre de sortie
+  pixedgeReg_1 : entity work.pixedgeReg
+    port map (
+      clk          => clk,
+      reset        => reset,
+	  I_pixEdge    => S_pixEdge,
+      I_ldPixEdge  => I_ldPixEdge,
+      O_pixEdge    => O_pixEdge);
+  
+end Behavioral;
+

src/pixedgeReg.vhd

+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity pixedgeReg is
+    Port ( clk			:in STD_LOGIC;
+		   reset		:in STD_LOGIC;
+		   I_pixEdge : in  STD_LOGIC;
+		   I_ldPixEdge : in STD_LOGIC;
+		   O_pixEdge : out  STD_LOGIC		   
+		   ); 
+end pixedgeReg;
+
+
+architecture Behavioral of pixedgeReg is
+
+-- déclaration des signaux internes
+	_BLANK_
+
+begin
+
+	
+	_BLANK_
+		
+
+end Behavioral;
+

src/regUnit.vhd

+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity regUnit is
+    Port ( clk			:in STD_LOGIC;
+	       reset		:in STD_LOGIC;
+		   I_pixel : in  STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
+           I_ldPix11 : in  STD_LOGIC;
+           I_ldPix21 : in  STD_LOGIC;
+           I_ldPix31 : in  STD_LOGIC;
+           I_shReg : in  STD_LOGIC;
+		   O_Pix11, O_Pix12, O_Pix13 : out STD_LOGIC_VECTOR (7 downto 0);
+		   O_Pix21, O_Pix22, O_Pix23 : out STD_LOGIC_VECTOR (7 downto 0);
+		   O_Pix31, O_Pix32, O_Pix33 : out STD_LOGIC_VECTOR (7 downto 0)		   
+		   ); 
+end regUnit;
+
+
+architecture Behavioral of regUnit is
+
+
+signal S_Pix11, S_Pix12, S_Pix13 : STD_LOGIC_VECTOR (7 downto 0);
+signal S_Pix21, S_Pix22, S_Pix23 : STD_LOGIC_VECTOR (7 downto 0);
+signal S_Pix31, S_Pix32, S_Pix33 : STD_LOGIC_VECTOR (7 downto 0);	
+
+begin
+
+	-- banc de registres
+	process(_BLANK_)
+	begin
+	if(reset = '1') then
+		S_Pix11 <= (others => '0');
+		S_Pix12 <= (others => '0');
+		S_Pix13 <= (others => '0');
+		S_Pix21 <= (others => '0');
+		S_Pix22 <= (others => '0');
+		S_Pix23 <= (others => '0');
+		S_Pix31 <= (others => '0');
+		S_Pix32 <= (others => '0');
+		S_Pix33 <= (others => '0');		
+	elsif(rising_edge(clk)) then
+	
+		_BLANK_
+		
+	end if;
+	end process;
+
+	-- Connecter les sorties des registres aux ports 
+	-- d’entrée/sortie du banc de registres 
+	O_Pix11 <= S_Pix11;
+	O_Pix12 <= S_Pix12;
+	O_Pix13 <= S_Pix13;
+	O_Pix21 <= S_Pix21;
+	O_Pix22 <= S_Pix22;
+	O_Pix23 <= S_Pix23;
+	O_Pix31 <= S_Pix31;
+	O_Pix32 <= S_Pix32;
+	O_Pix33 <= S_Pix33;
+	
+end Behavioral;
+

src/sobelProc.vhd

+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity  sobelProc is
+    Port ( clk				: in STD_LOGIC;
+		   reset			: in STD_LOGIC;
+		   I_go	   			: in STD_LOGIC;
+		   -- interface avec la mémoire IN (lecture)
+		   O_enM_R		 	: out STD_LOGIC;
+		   O_ADR_R		 	: out STD_LOGIC_VECTOR (13 downto 0); 
+		   I_pixel 			: in  STD_LOGIC_VECTOR (7 downto 0); -- Pixel from memory IN
+		   -- interface avec la mémoire OUT (écriture)
+		   O_enM_W		 	: out STD_LOGIC;		   
+		   O_ADR_W	 	 	: out STD_LOGIC_VECTOR (13 downto 0); 
+		   O_pixEdge 		: out  STD_LOGIC; -- Edge to memory OUT
+		   -- signal de commande vers le contrôleur VGA		   		   
+		   O_StartDisplay	: out STD_LOGIC
+		   ); 
+end  sobelProc;
+
+
+architecture Behavioral of  sobelProc is
+
+-- déclaration des sous-composants
+
+  -- unité opérative 
+  component operativeUnit is
+    port (clk,reset	:in STD_LOGIC;
+		  I_pixel : in  STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
+          I_ldPix11 : in  STD_LOGIC;
+          I_ldPix21 : in  STD_LOGIC;
+          I_ldPix31 : in  STD_LOGIC;
+          I_shReg : in  STD_LOGIC;
+		  I_ldPixEdge : in STD_LOGIC;
+		  O_pixEdge : out  STD_LOGIC	
+		  );
+  end component operativeUnit;
+  
+  -- générateur d'adresses
+  component adrgenUnit is
+    port ( clk,reset	 : in STD_LOGIC;
+		   I_clr_PtrLine : in STD_LOGIC;
+		   I_inc_PtrLine : in STD_LOGIC;
+		   I_clr_PtrCol  : in STD_LOGIC;
+		   I_inc_PtrCol  : in STD_LOGIC;
+		   I_selPix 	 : in STD_LOGIC_VECTOR (1 downto 0);
+		   O_EndImage	 : out STD_LOGIC;
+		   O_NewLine	 : out STD_LOGIC;
+		   O_ADR_R		 : out STD_LOGIC_VECTOR (13 downto 0);
+		   O_ADR_W	 	 : out STD_LOGIC_VECTOR (13 downto 0)   
+		   );
+  end component adrgenUnit;
+  
+  -- automate
+  component automate is
+    Port (clk,reset	 : in STD_LOGIC;
+		   I_go	   		 : in STD_LOGIC;
+		   I_EndImage	 : in STD_LOGIC;
+		   I_NewLine	 : in STD_LOGIC;
+		   -- signaux de commandes vers l'unité opérative
+           O_ldPix11 	 : out  STD_LOGIC;
+           O_ldPix21 	 : out  STD_LOGIC;
+           O_ldPix31 	 : out  STD_LOGIC;
+           O_shReg 		 : out  STD_LOGIC;
+		   O_ldPixEdge 	 : out STD_LOGIC;
+		   -- signaux de commandes vers le générateur d'adresses		   
+		   O_clr_PtrLine : out STD_LOGIC;
+		   O_inc_PtrLine : out STD_LOGIC;
+		   O_clr_PtrCol  : out STD_LOGIC;
+		   O_inc_PtrCol  : out STD_LOGIC;
+		   O_selPix 	 : out STD_LOGIC_VECTOR (1 downto 0);		   
+		   -- signaux de commandes vers les mémoires		   
+		   O_enM_R		 : out STD_LOGIC;
+		   O_enM_W		 : out STD_LOGIC;
+		   -- signal de commande vers le contrôleur VGA		   		   
+		   O_StartDisplay  : out STD_LOGIC		   
+		   ); 
+  end component automate;
+ 
+-- déclaration des signaux internes
+signal S_EndImage	 	: STD_LOGIC;
+signal S_NewLine	 	: STD_LOGIC;
+signal S_ldPix11 	 	: STD_LOGIC;
+signal S_ldPix21 	 	: STD_LOGIC;
+signal S_ldPix31 	 	: STD_LOGIC;
+signal S_shReg 	 	: STD_LOGIC;
+signal S_ldPixEdge		: STD_LOGIC;
+signal S_clr_PtrLine 	: STD_LOGIC;
+signal S_inc_PtrLine 	: STD_LOGIC;
+signal S_clr_PtrCol  	: STD_LOGIC;
+signal S_inc_PtrCol  	: STD_LOGIC;
+signal S_selPix 	 	: STD_LOGIC_VECTOR (1 downto 0);		   
+		   
+
+begin
+
+-- instanciation des sous-composants et établissement des interconnexions
+  
+  -- instanciation de l'unité opérative
+  operativeUnit_1 : entity work.operativeUnit
+    port map (
+      clk          => clk,
+      reset        => reset,
+	  I_pixel      => I_pixel, 
+	  I_ldPix11    => S_ldPix11,
+	  I_ldPix21    => S_ldPix21,
+	  I_ldPix31    => S_ldPix31,
+	  I_shReg      => S_shReg,
+	  I_ldPixEdge  => S_ldPixEdge,
+	  O_pixEdge    => O_pixEdge
+	  );
+	  
+  -- instanciation du générateur d'adresses 
+  adrgenUnit_1 : entity work.adrgenUnit
+    port map (
+      clk           => clk,
+      reset         => reset,
+	  I_clr_PtrLine => S_clr_PtrLine, 
+      I_inc_PtrLine => S_inc_PtrLine,
+      I_clr_PtrCol  => S_clr_PtrCol,
+      I_inc_PtrCol  => S_inc_PtrCol, 
+	  I_selPix 	    => S_selPix, 
+	  O_EndImage	=> S_EndImage,	
+	  O_NewLine	    => S_NewLine, 
+	  O_ADR_R		=> O_ADR_R,	
+	  O_ADR_W	 	=> O_ADR_W
+	  );
+	  
+  -- instanciation de l'automate
+  automate_1 : entity work.automate
+    port map (
+      clk           => clk,
+      reset         => reset,
+	  I_go	   		 => I_go,
+	  I_EndImage	 => S_EndImage,	 
+	  I_NewLine	     => S_NewLine,	 
+      O_ldPix11 	 => S_ldPix11, 	 
+      O_ldPix21 	 => S_ldPix21, 	 
+      O_ldPix31 	 => S_ldPix31, 	 
+      O_shReg 		 => S_shReg, 		 
+      O_ldPixEdge 	 => S_ldPixEdge, 	 
+      O_clr_PtrLine  => S_clr_PtrLine, 
+      O_inc_PtrLine  => S_inc_PtrLine, 
+      O_clr_PtrCol   => S_clr_PtrCol, 
+      O_inc_PtrCol   => S_inc_PtrCol,  
+      O_selPix 	     => S_selPix, 	 
+      O_enM_R		 => O_enM_R,		 
+      O_enM_W		 => O_enM_W,		 
+      O_StartDisplay => O_StartDisplay
+      );
+  
+end Behavioral;
+