report.md

Soble Lab Report

Name: Name:

Question 1: What is the nature of the VHDL process that describes the register bank? Its sensitivity list? Did the functional simulation validate the module? Justify

Question 2: Give the results obtained

Question 3: What type and quantification did you use for the internal signals? Justify.

Question 4: How many processes are used and what are their natures? Sensitivity list? Did the functional simulation validate the module? Justify

Question 5: Give the results obtained

Question 6: Did the functional simulation validate the module? Justify

Question 7: Give and comment on the results obtained

Question 8: Give the architecture you propose for the address generator

Question 9: Did the functional simulation validate the module? Justify

Question 10: Give the results obtained

Question 11: Complete the state machine diagram

!!! info This diagram is to be completed in order to then complete the VHDL file automate.vhd. To do this, you can use the file automate.drawio available in the git repository, it is the file docs/img/automate.drawio with the tool https://app.diagrams.net/. Then update the file automate.png by exporting the diagram automate.drawio previously updated.

Question 12: How many processes are used to describe the FSM, and what are their natures? Their sensitivity lists? Did the functional simulation validate the module? Justify

Question 13: Give the results obtained

Question 14: Did the functional simulation validate the module? Justify

Question 15: Give and comment on the results obtained. What is the percentage of resources used by the Sobel processor compared to those available on the target Artix 7 FPGA XC7A100T-CSG324-1. Comment

Question 16: Give and comment on the results obtained.