Add readme add VHDL source archive

README.md

docs/img/.$sobel-FSM.drawio.bkp

docs/img/sobel-FSM.drawio

docs/img/sobel-FSM.png

docs/report.md

docs/report.md~

src/DualPortRamGeneric.vhd

src/Nexys4_Sobel.xdc

src/SinglePortROMFileInitGeneric.vhd

src/adrgenUnit.vhd

src/automate.vhd

src/dancing_spider.txt

src/gradientUnit.vhd

src/ip/clk_wiz_vga_25MHz/clk_wiz_vga_25MHz.vho

src/ip/clk_wiz_vga_25MHz/clk_wiz_vga_25MHz.xci

src/ip/clk_wiz_vga_25MHz/clk_wiz_vga_25MHz.xml

src/operativeUnit.vhd

src/pixedgeReg.vhd

src/regUnit.vhd

src/sobelProc.vhd