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Commit 1f975319 authored by Zhaojun SUN's avatar Zhaojun SUN
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feat: assembled echo and filter

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......@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Mar 14 14:21:45 2023">
<application name="pa" timeStamp="Tue Mar 14 14:52:06 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="37857ad2172d46c5b738a74a55aca26a" type="ProjectID"/>
<property name="ProjectIteration" value="14" type="ProjectIteration"/>
<property name="ProjectIteration" value="15" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
......@@ -17,42 +17,44 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="3" type="JavaHandler"/>
<property name="AutoConnectTarget" value="3" type="JavaHandler"/>
<property name="AddSources" value="4" type="JavaHandler"/>
<property name="AutoConnectTarget" value="4" type="JavaHandler"/>
<property name="CloseProject" value="1" type="JavaHandler"/>
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="EditPaste" value="1" type="JavaHandler"/>
<property name="EditUndo" value="1" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="3" type="JavaHandler"/>
<property name="OpenHardwareManager" value="4" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="5" type="JavaHandler"/>
<property name="OpenHardwareManager" value="5" type="JavaHandler"/>
<property name="ProgramDevice" value="1" type="JavaHandler"/>
<property name="ResetLayout" value="3" type="JavaHandler"/>
<property name="RunBitgen" value="13" type="JavaHandler"/>
<property name="RunSynthesis" value="1" type="JavaHandler"/>
<property name="RunBitgen" value="14" type="JavaHandler"/>
<property name="RunSynthesis" value="3" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="5" type="JavaHandler"/>
<property name="SetSourceEnabled" value="3" type="JavaHandler"/>
<property name="SetTopNode" value="9" type="JavaHandler"/>
<property name="SetTopNode" value="10" type="JavaHandler"/>
<property name="ShowSource" value="1" type="JavaHandler"/>
<property name="ShowView" value="8" type="JavaHandler"/>
<property name="SimulationBreak" value="1" type="JavaHandler"/>
<property name="SimulationRelaunch" value="18" type="JavaHandler"/>
<property name="SimulationRestart" value="16" type="JavaHandler"/>
<property name="SimulationRun" value="7" type="JavaHandler"/>
<property name="SimulationRunForTime" value="19" type="JavaHandler"/>
<property name="SimulationRestart" value="22" type="JavaHandler"/>
<property name="SimulationRun" value="9" type="JavaHandler"/>
<property name="SimulationRunAll" value="1" type="JavaHandler"/>
<property name="SimulationRunForTime" value="53" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="2" type="JavaHandler"/>
<property name="UpdateSourceFiles" value="1" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="2" type="JavaHandler"/>
<property name="ba" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="AbstractFileView_RELOAD" value="2" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="32" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="11" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="35" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="12" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="6" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="306" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="27" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="23" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="312" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="36" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="24" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="6" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="8" type="GuiHandlerData"/>
<property name="HCodeEditor_BLANK_OPERATIONS" value="2" type="GuiHandlerData"/>
......@@ -67,46 +69,48 @@ This means code written to parse this file will need to be revisited each subseq
<property name="MainMenuMgr_FLOW" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="62" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="65" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="14" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="15" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_INSTANTIATION" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_IMPORT_SRC" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="9" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_LIVE_RESTART" value="16" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_LIVE_RUN" value="20" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="10" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_LIVE_BREAK" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_LIVE_RESTART" value="22" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_LIVE_RUN" value="58" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_LIVE_RUN_ALL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="20" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="7" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="9" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_DISABLE" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_REPLACE_FILE" value="1" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="16" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
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<property name="ProgramDebugTab_OPEN_TARGET" value="3" type="GuiHandlerData"/>
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<property name="PAViews_PROJECT_SUMMARY" value="10" type="GuiHandlerData"/>
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<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="3" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="15" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="16" type="GuiHandlerData"/>
<property name="SrcMenu_REFRESH_HIERARCHY" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="3" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="4" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="5" type="GuiHandlerData"/>
<property name="WaveformFindBar_RADIX" value="2" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="53" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="92" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_TIME_0" value="3" type="GuiHandlerData"/>
</item>
</section>
......
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
......@@ -66,6 +66,7 @@ set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param chipscope.maxJobs 1
set_param xicom.use_bs_reader 1
create_project -in_memory -part xc7a200tsbg484-1
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
......@@ -75,10 +76,9 @@ set rc [catch {
update_ip_catalog
set_property ip_output_repo /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1/audioProc.dcp
read_ip -quiet /homes/z22sun/FPGA/MiniProjet/src/ip/clk_wiz_0/clk_wiz_0.xci
add_files -quiet /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1/firUnit.dcp
read_xdc /homes/z22sun/FPGA/MiniProjet/src/constraints/NexysVideo_Master.xdc
link_design -top audioProc -part xc7a200tsbg484-1
link_design -top firUnit -part xc7a200tsbg484-1
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
......@@ -94,8 +94,8 @@ set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force audioProc_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx"
write_checkpoint -force firUnit_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file firUnit_drc_opted.rpt -pb firUnit_drc_opted.pb -rpx firUnit_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
......@@ -114,10 +114,10 @@ set rc [catch {
implement_debug_core
}
place_design
write_checkpoint -force audioProc_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file audioProc_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file audioProc_control_sets_placed.rpt"
write_checkpoint -force firUnit_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file firUnit_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file firUnit_utilization_placed.rpt -pb firUnit_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file firUnit_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
......@@ -133,19 +133,19 @@ set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force audioProc_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file audioProc_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx"
write_checkpoint -force firUnit_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file firUnit_drc_routed.rpt -pb firUnit_drc_routed.pb -rpx firUnit_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file firUnit_methodology_drc_routed.rpt -pb firUnit_methodology_drc_routed.pb -rpx firUnit_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file firUnit_power_routed.rpt -pb firUnit_power_summary_routed.pb -rpx firUnit_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file firUnit_route_status.rpt -pb firUnit_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file firUnit_timing_summary_routed.rpt -pb firUnit_timing_summary_routed.pb -rpx firUnit_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file firUnit_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file firUnit_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file firUnit_bus_skew_routed.rpt -pb firUnit_bus_skew_routed.pb -rpx firUnit_bus_skew_routed.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force audioProc_routed_error.dcp
write_checkpoint -force firUnit_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
......@@ -157,10 +157,10 @@ start_step write_bitstream
set ACTIVE_STEP write_bitstream
set rc [catch {
create_msg_db write_bitstream.pb
catch { write_mem_info -force audioProc.mmi }
write_bitstream -force audioProc.bit -bin_file
catch {write_debug_probes -quiet -force audioProc}
catch {file copy -force audioProc.ltx debug_nets.ltx}
catch { write_mem_info -force firUnit.mmi }
write_bitstream -force firUnit.bit -bin_file
catch {write_debug_probes -quiet -force firUnit}
catch {file copy -force firUnit.ltx debug_nets.ltx}
close_msg_db -file write_bitstream.pb
} RESULT]
if {$rc} {
......
This diff is collapsed.
File added
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
| Date : Tue Mar 14 14:55:19 2023
| Host : pc-elec-191 running 64-bit Ubuntu 20.04.5 LTS
| Command : report_bus_skew -warn_on_violation -file firUnit_bus_skew_routed.rpt -pb firUnit_bus_skew_routed.pb -rpx firUnit_bus_skew_routed.rpx
| Design : firUnit
| Device : 7a200t-sbg484
| Speed File : -1 PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
| Date : Tue Mar 14 14:55:19 2023
| Host : pc-elec-191 running 64-bit Ubuntu 20.04.5 LTS
| Command : report_clock_utilization -file firUnit_clock_utilization_routed.rpt
| Design : firUnit
| Device : 7a200t-sbg484
| Speed File : -1 PRODUCTION 1.23 2018-06-13
| Design State : Routed
-------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X0Y1
8. Clock Region Cell Placement per Global Clock: Region X0Y2
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 120 | 0 | 0 | 0 |
| BUFIO | 0 | 40 | 0 | 0 | 0 |
| BUFMR | 0 | 20 | 0 | 0 | 0 |
| BUFR | 0 | 40 | 0 | 0 | 0 |
| MMCM | 0 | 10 | 0 | 0 | 0 |
| PLL | 0 | 10 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------+-------------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------+-------------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 2 | 257 | 0 | | | I_clock_IBUF_BUFG_inst/O | I_clock_IBUF_BUFG |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------+-------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+---------------------+--------------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+---------------------+--------------+
| src0 | g0 | IBUF/O | None | IOB_X0Y128 | X0Y2 | 1 | 0 | | | I_clock_IBUF_inst/O | I_clock_IBUF |
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+---------------------+--------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 800 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 16 | 4200 | 16 | 1400 | 0 | 100 | 3 | 50 | 0 | 100 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 213 | 3600 | 86 | 1400 | 0 | 100 | 11 | 50 | 0 | 100 |
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
| X1Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 0 | 2550 | 0 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
| X1Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 1 | 0 |
| Y1 | 1 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------+
| g0 | BUFG/O | n/a | | | | 243 | 0 | 0 | 0 | I_clock_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+------+----+
| | X0 | X1 |
+----+------+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 224 | 0 |
| Y1 | 19 | 0 |
| Y0 | 0 | 0 |
+----+------+----+
7. Clock Region Cell Placement per Global Clock: Region X0Y1
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
| g0 | n/a | BUFG/O | None | 19 | 0 | 16 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | I_clock_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
8. Clock Region Cell Placement per Global Clock: Region X0Y2
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------+
| g0 | n/a | BUFG/O | None | 224 | 0 | 213 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | I_clock_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y0 [get_cells I_clock_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X0Y128 [get_ports I_clock]
# Clock net "I_clock_IBUF_BUFG" driven by instance "I_clock_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_I_clock_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_I_clock_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="I_clock_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_I_clock_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}
#endgroup
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
| Date : Tue Mar 14 14:54:30 2023
| Host : pc-elec-191 running 64-bit Ubuntu 20.04.5 LTS
| Command : report_control_sets -verbose -file firUnit_control_sets_placed.rpt
| Design : firUnit
| Device : xc7a200t
------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Total control sets | 10 |
| Minimum number of control sets | 10 |
| Addition due to synthesis replication | 0 |
| Addition due to physical synthesis replication | 0 |
| Unused register locations in slices containing registers | 22 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions
2. Histogram
------------
+--------------------+-------+
| Fanout | Count |
+--------------------+-------+
| Total control sets | 10 |
| >= 0 to < 4 | 1 |
| >= 4 to < 6 | 2 |
| >= 6 to < 8 | 1 |
| >= 8 to < 10 | 2 |
| >= 10 to < 12 | 1 |
| >= 12 to < 14 | 0 |
| >= 14 to < 16 | 1 |
| >= 16 | 2 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 6 | 4 |
| No | No | Yes | 10 | 4 |
| No | Yes | No | 0 | 0 |
| Yes | No | No | 23 | 5 |
| Yes | No | Yes | 195 | 55 |
| Yes | Yes | No | 0 | 0 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+-----------------------------------+--------------------------------------------------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+-----------------------------------+--------------------------------------------------------+------------------+------------------+----------------+
| I_clock_IBUF_BUFG | | | 1 | 1 |
| I_clock_IBUF_BUFG | controlUnit_filter/Q[1] | I_reset_IBUF | 2 | 4 |
| controlUnit_filter/SR_futurState | | | 3 | 5 |
| I_clock_IBUF_BUFG | controlUnit_filter/Q[2] | | 2 | 7 |
| I_clock_IBUF_BUFG | controlUnit_echo/Q[1] | | 2 | 8 |
| I_clock_IBUF_BUFG | controlUnit_echo/E[0] | | 1 | 8 |
| I_clock_IBUF_BUFG | | I_reset_IBUF | 4 | 10 |
| I_clock_IBUF_BUFG | controlUnit_filter/FSM_onehot_SR_presentState_reg[1]_0 | I_reset_IBUF | 4 | 15 |
| I_clock_IBUF_BUFG | controlUnit_echo/Q[0] | I_reset_IBUF | 14 | 48 |
| I_clock_IBUF_BUFG | controlUnit_filter/Q[0] | I_reset_IBUF | 35 | 128 |
+-----------------------------------+--------------------------------------------------------+------------------+------------------+----------------+
File added
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
| Date : Tue Mar 14 14:54:25 2023
| Host : pc-elec-191 running 64-bit Ubuntu 20.04.5 LTS
| Command : report_drc -file firUnit_drc_opted.rpt -pb firUnit_drc_opted.pb -rpx firUnit_drc_opted.rpx
| Design : firUnit
| Device : xc7a200tsbg484-1
| Speed File : -1
| Design State : Synthesized
------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 24
+-----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
| CHECK-3 | Warning | Report rule limit reached | 1 |
| REQP-1839 | Warning | RAMB36 async control check | 20 |
+-----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
20 out of 20 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: I_inputSample[7:0], O_filteredSample[7:0], I_clock, I_inputSampleValid, I_reset, O_filteredSampleValid.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
20 out of 20 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: I_inputSample[7:0], O_filteredSample[7:0], I_clock, I_inputSampleValid, I_reset, O_filteredSampleValid.
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
CHECK-3#1 Warning
Report rule limit reached
REQP-1839 rule limit reached: 20 violations have been found.
Related violations: <none>
REQP-1839#1 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[0] (net: operativeUnit_echo/bufferWriteAddress_reg[0]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#2 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[10] (net: operativeUnit_echo/bufferWriteAddress_reg[10]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#3 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[11] (net: operativeUnit_echo/bufferWriteAddress_reg[11]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#4 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[12] (net: operativeUnit_echo/bufferWriteAddress_reg[12]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#5 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[13] (net: operativeUnit_echo/bufferWriteAddress_reg[13]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#6 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[14] (net: operativeUnit_echo/bufferWriteAddress_reg[14]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#7 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[15] (net: operativeUnit_echo/bufferWriteAddress_reg[15]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#8 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[1] (net: operativeUnit_echo/bufferWriteAddress_reg[1]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#9 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[2] (net: operativeUnit_echo/bufferWriteAddress_reg[2]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#10 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[3] (net: operativeUnit_echo/bufferWriteAddress_reg[3]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#11 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[4] (net: operativeUnit_echo/bufferWriteAddress_reg[4]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#12 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[5] (net: operativeUnit_echo/bufferWriteAddress_reg[5]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#13 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[6] (net: operativeUnit_echo/bufferWriteAddress_reg[6]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#14 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[7] (net: operativeUnit_echo/bufferWriteAddress_reg[7]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#15 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[8] (net: operativeUnit_echo/bufferWriteAddress_reg[8]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#16 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[9] (net: operativeUnit_echo/bufferWriteAddress_reg[9]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#17 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRBWRADDR[12] (net: operativeUnit_echo/bufferReadAddress[12]) which is driven by a register (operativeUnit_echo/bufferReadAddress_reg_rep[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#18 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRBWRADDR[13] (net: operativeUnit_echo/bufferReadAddress[13]) which is driven by a register (operativeUnit_echo/bufferReadAddress_reg_rep[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#19 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRBWRADDR[14] (net: operativeUnit_echo/bufferReadAddress[14]) which is driven by a register (operativeUnit_echo/bufferReadAddress_reg_rep[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#20 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRBWRADDR[15] (net: operativeUnit_echo/bufferReadAddress[15]) which is driven by a register (operativeUnit_echo/bufferReadAddress_reg_rep[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
File added
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
| Date : Tue Mar 14 14:55:15 2023
| Host : pc-elec-191 running 64-bit Ubuntu 20.04.5 LTS
| Command : report_drc -file firUnit_drc_routed.rpt -pb firUnit_drc_routed.pb -rpx firUnit_drc_routed.rpx
| Design : firUnit
| Device : xc7a200tsbg484-1
| Speed File : -1
| Design State : Fully Routed
---------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 25
+-----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
| CHECK-3 | Warning | Report rule limit reached | 1 |
| PDRC-153 | Warning | Gated clock check | 1 |
| REQP-1839 | Warning | RAMB36 async control check | 20 |
+-----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
20 out of 20 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: I_inputSample[7:0], O_filteredSample[7:0], I_clock, I_inputSampleValid, I_reset, O_filteredSampleValid.
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
20 out of 20 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: I_inputSample[7:0], O_filteredSample[7:0], I_clock, I_inputSampleValid, I_reset, O_filteredSampleValid.
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
CHECK-3#1 Warning
Report rule limit reached
REQP-1839 rule limit reached: 20 violations have been found.
Related violations: <none>
PDRC-153#1 Warning
Gated clock check
Net controlUnit_filter/SR_futurState is a gated clock net sourced by a combinational pin controlUnit_filter/FSM_onehot_SR_futurState_reg[4]_i_2/O, cell controlUnit_filter/FSM_onehot_SR_futurState_reg[4]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>
REQP-1839#1 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[0] (net: operativeUnit_echo/bufferWriteAddress_reg[0]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#2 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[10] (net: operativeUnit_echo/bufferWriteAddress_reg[10]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#3 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[11] (net: operativeUnit_echo/bufferWriteAddress_reg[11]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#4 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[12] (net: operativeUnit_echo/bufferWriteAddress_reg[12]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#5 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[13] (net: operativeUnit_echo/bufferWriteAddress_reg[13]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#6 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[14] (net: operativeUnit_echo/bufferWriteAddress_reg[14]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#7 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[15] (net: operativeUnit_echo/bufferWriteAddress_reg[15]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#8 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[1] (net: operativeUnit_echo/bufferWriteAddress_reg[1]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#9 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[2] (net: operativeUnit_echo/bufferWriteAddress_reg[2]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#10 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[3] (net: operativeUnit_echo/bufferWriteAddress_reg[3]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#11 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[4] (net: operativeUnit_echo/bufferWriteAddress_reg[4]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#12 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[5] (net: operativeUnit_echo/bufferWriteAddress_reg[5]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#13 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[6] (net: operativeUnit_echo/bufferWriteAddress_reg[6]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#14 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[7] (net: operativeUnit_echo/bufferWriteAddress_reg[7]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#15 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[8] (net: operativeUnit_echo/bufferWriteAddress_reg[8]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#16 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRARDADDR[9] (net: operativeUnit_echo/bufferWriteAddress_reg[9]) which is driven by a register (operativeUnit_echo/bufferWriteAddress_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#17 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRBWRADDR[12] (net: operativeUnit_echo/bufferReadAddress[12]) which is driven by a register (operativeUnit_echo/bufferReadAddress_reg_rep[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#18 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRBWRADDR[13] (net: operativeUnit_echo/bufferReadAddress[13]) which is driven by a register (operativeUnit_echo/bufferReadAddress_reg_rep[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#19 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRBWRADDR[14] (net: operativeUnit_echo/bufferReadAddress[14]) which is driven by a register (operativeUnit_echo/bufferReadAddress_reg_rep[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#20 Warning
RAMB36 async control check
The RAMB36E1 operativeUnit_echo/soundBuffer_reg_0_1 has an input control pin operativeUnit_echo/soundBuffer_reg_0_1/ADDRBWRADDR[15] (net: operativeUnit_echo/bufferReadAddress[15]) which is driven by a register (operativeUnit_echo/bufferReadAddress_reg_rep[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
| Date : Tue Mar 14 14:55:18 2023
| Host : pc-elec-191 running 64-bit Ubuntu 20.04.5 LTS
| Command : report_power -file firUnit_power_routed.rpt -pb firUnit_power_summary_routed.pb -rpx firUnit_power_routed.rpx
| Design : firUnit
| Device : xc7a200tsbg484-1
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
-------------------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 2.147 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 2.004 |
| Device Static (W) | 0.143 |
| Effective TJA (C/W) | 3.3 |
| Max Ambient (C) | 77.9 |
| Junction Temperature (C) | 32.1 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 0.582 | 540 | --- | --- |
| LUT as Logic | 0.462 | 218 | 133800 | 0.16 |
| CARRY4 | 0.105 | 31 | 33450 | 0.09 |
| BUFG | 0.006 | 1 | 32 | 3.13 |
| Register | 0.006 | 234 | 267600 | 0.09 |
| F7/F8 Muxes | 0.004 | 24 | 133800 | 0.02 |
| Others | 0.000 | 13 | --- | --- |
| Signals | 0.512 | 420 | --- | --- |
| Block RAM | 0.393 | 14 | 365 | 3.84 |
| I/O | 0.517 | 20 | 285 | 7.02 |
| Static Power | 0.143 | | | |
| Total | 2.147 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 1.000 | 1.535 | 1.495 | 0.040 |
| Vccaux | 1.800 | 0.071 | 0.039 | 0.031 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.231 | 0.226 | 0.005 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 1.000 | 0.033 | 0.032 | 0.001 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 3.3 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 4.6 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+------------------------+-----------+
| Name | Power (W) |
+------------------------+-----------+
| firUnit | 2.004 |
| controlUnit_echo | 0.036 |
| controlUnit_filter | 0.007 |
| operativeUnit_echo | 0.553 |
| operativeUnit_filter | 0.809 |
+------------------------+-----------+
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