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Commit 2e4f7ad8 authored by Zhaojun SUN's avatar Zhaojun SUN
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feat: assembled echo and filter

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......@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Mar 14 09:46:21 2023">
<application name="pa" timeStamp="Tue Mar 14 14:21:45 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="37857ad2172d46c5b738a74a55aca26a" type="ProjectID"/>
<property name="ProjectIteration" value="7" type="ProjectIteration"/>
<property name="ProjectIteration" value="14" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
......@@ -17,17 +17,23 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="3" type="JavaHandler"/>
<property name="AutoConnectTarget" value="3" type="JavaHandler"/>
<property name="CloseProject" value="1" type="JavaHandler"/>
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="EditPaste" value="1" type="JavaHandler"/>
<property name="EditUndo" value="1" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="3" type="JavaHandler"/>
<property name="OpenHardwareManager" value="4" type="JavaHandler"/>
<property name="ProgramDevice" value="1" type="JavaHandler"/>
<property name="ResetLayout" value="3" type="JavaHandler"/>
<property name="RunBitgen" value="6" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="2" type="JavaHandler"/>
<property name="RunBitgen" value="13" type="JavaHandler"/>
<property name="RunSynthesis" value="1" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="5" type="JavaHandler"/>
<property name="SetSourceEnabled" value="3" type="JavaHandler"/>
<property name="SetTopNode" value="9" type="JavaHandler"/>
<property name="ShowView" value="1" type="JavaHandler"/>
<property name="ShowSource" value="1" type="JavaHandler"/>
<property name="ShowView" value="8" type="JavaHandler"/>
<property name="SimulationRelaunch" value="18" type="JavaHandler"/>
<property name="SimulationRestart" value="16" type="JavaHandler"/>
<property name="SimulationRun" value="7" type="JavaHandler"/>
......@@ -40,12 +46,12 @@ This means code written to parse this file will need to be revisited each subseq
<item name="Gui Handlers">
<property name="AbstractFileView_RELOAD" value="2" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="15" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="4" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="32" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="11" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="6" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="217" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="19" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="306" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="27" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="23" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="6" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="8" type="GuiHandlerData"/>
......@@ -55,9 +61,17 @@ This means code written to parse this file will need to be revisited each subseq
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="1" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_BLOCK_COMMENTS" value="2" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="5" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="2" type="GuiHandlerData"/>
<property name="HJFileChooserHelpers_REFRESH_FOLDER_VIEW_TO_REFLECT_EXTERNAL" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="62" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="11" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="14" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_INSTANTIATION" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_IMPORT_SRC" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="9" type="GuiHandlerData"/>
......@@ -68,22 +82,26 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PACommandNames_SRC_DISABLE" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_REPLACE_FILE" value="1" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="8" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="16" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="6" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="7" type="GuiHandlerData"/>
<property name="ProgramDebugTab_OPEN_TARGET" value="3" type="GuiHandlerData"/>
<property name="ProgramDebugTab_PROGRAM_DEVICE" value="2" type="GuiHandlerData"/>
<property name="ProgramFpgaDialog_PROGRAM" value="3" type="GuiHandlerData"/>
<property name="RDICommands_COPY" value="10" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RDICommands_LINE_COMMENT" value="1" type="GuiHandlerData"/>
<property name="RDICommands_PASTE" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="1" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="30" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="3" type="GuiHandlerData"/>
<property name="SimulationLiveRunForComp_SPECIFY_TIME_AND_UNITS" value="3" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="27" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="17" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="13" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="3" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="15" type="GuiHandlerData"/>
<property name="SrcMenu_REFRESH_HIERARCHY" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="3" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="5" type="GuiHandlerData"/>
......@@ -91,11 +109,6 @@ This means code written to parse this file will need to be revisited each subseq
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="53" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_TIME_0" value="3" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="13" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="6" type="TclMode"/>
</item>
</section>
</application>
</document>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
......@@ -61,14 +61,102 @@ proc step_failed { step } {
}
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param chipscope.maxJobs 1
create_project -in_memory -part xc7a200tsbg484-1
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.cache/wt [current_project]
set_property parent.project_path /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.xpr [current_project]
set_property ip_repo_paths /homes/z22sun/FPGA/MiniProjet/repo [current_project]
update_ip_catalog
set_property ip_output_repo /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/synth_1/audioProc.dcp
read_ip -quiet /homes/z22sun/FPGA/MiniProjet/src/ip/clk_wiz_0/clk_wiz_0.xci
read_xdc /homes/z22sun/FPGA/MiniProjet/src/constraints/NexysVideo_Master.xdc
link_design -top audioProc -part xc7a200tsbg484-1
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force audioProc_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
if { [llength [get_debug_cores -quiet] ] > 0 } {
implement_debug_core
}
place_design
write_checkpoint -force audioProc_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file audioProc_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file audioProc_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force audioProc_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file audioProc_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force audioProc_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
start_step write_bitstream
set ACTIVE_STEP write_bitstream
set rc [catch {
create_msg_db write_bitstream.pb
set_param chipscope.maxJobs 1
set_param xicom.use_bs_reader 1
open_checkpoint audioProc_routed.dcp
set_property webtalk.parent_dir /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.cache/wt [current_project]
catch { write_mem_info -force audioProc.mmi }
write_bitstream -force audioProc.bit -bin_file
catch {write_debug_probes -quiet -force audioProc}
......
This diff is collapsed.
#-----------------------------------------------------------
# Vivado v2019.2 (64-bit)
# SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
# IP Build 2699827 on Thu Oct 24 21:16:38 MDT 2019
# Start of session at: Tue Mar 7 16:41:33 2023
# Process ID: 174478
# Current directory: /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1
# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
# Log file: /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1/audioProc.vdi
# Journal file: /homes/z22sun/FPGA/MiniProjet/proj/AudioProc.runs/impl_1/vivado.jou
#-----------------------------------------------------------
source audioProc.tcl -notrace
*** Halting run - EA reset detected ***
while executing
"start_step write_bitstream"
(file "audioProc.tcl" line 64)
INFO: [Common 17-206] Exiting Vivado at Tue Mar 7 16:41:50 2023...
File deleted
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
| Date : Tue Mar 7 15:55:31 2023
| Host : pc-elec-191 running 64-bit Ubuntu 20.04.5 LTS
| Command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
| Design : audioProc
| Device : 7a200t-sbg484
| Speed File : -1 PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints
This diff is collapsed.
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
| Date : Tue Mar 7 15:54:40 2023
| Host : pc-elec-191 running 64-bit Ubuntu 20.04.5 LTS
| Command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
| Design : audioProc
| Device : xc7a200t
--------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Total control sets | 29 |
| Minimum number of control sets | 29 |
| Addition due to synthesis replication | 0 |
| Addition due to physical synthesis replication | 0 |
| Unused register locations in slices containing registers | 65 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions
2. Histogram
------------
+--------------------+-------+
| Fanout | Count |
+--------------------+-------+
| Total control sets | 29 |
| >= 0 to < 4 | 3 |
| >= 4 to < 6 | 6 |
| >= 6 to < 8 | 3 |
| >= 8 to < 10 | 6 |
| >= 10 to < 12 | 1 |
| >= 12 to < 14 | 1 |
| >= 14 to < 16 | 0 |
| >= 16 | 9 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 28 | 21 |
| No | No | Yes | 10 | 5 |
| No | Yes | No | 44 | 14 |
| Yes | No | No | 96 | 35 |
| Yes | No | Yes | 96 | 29 |
| Yes | Yes | No | 125 | 36 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+----------------------+-----------------------------------------------------------+-----------------------------------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------------+-----------------------------------------------------------+-----------------------------------------------+------------------+----------------+
| clk_1/inst/clk_out4 | rstn_IBUF | initialize_audio/data_i[4]_i_1_n_0 | 1 | 1 |
| clk_1/inst/clk_out1 | dbuttons/IV[2]_i_1_n_0 | | 1 | 1 |
| clk_1/inst/clk_out4 | rstn_IBUF | | 2 | 3 |
| clk_1/inst/clk_out4 | initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0 | | 2 | 4 |
| clk_1/inst/clk_out4 | initialize_audio/twi_controller/E[0] | rightFir/firUnit_1/operativeUnit_1/rstn | 1 | 4 |
| clk_1/inst/clk_out1 | lrclkcnt[3]_i_2_n_0 | lrclkcnt[3]_i_1_n_0 | 1 | 4 |
| clk_1/inst/clk_out4 | rstn_IBUF | initialize_audio/data_i[5]_i_1_n_0 | 1 | 4 |
| clk_1/inst/clk_out1 | audio_inout/BCLK_Fall_int | rightFir/firUnit_1/operativeUnit_1/rstn | 2 | 5 |
| clk_1/inst/clk_out1 | | audio_inout/Cnt_Bclk[4]_i_1_n_0 | 2 | 5 |
| clk_1/inst/clk_out4 | initialize_audio/twi_controller/sclCnt[6]_i_2_n_0 | initialize_audio/twi_controller/sclCnt0_1 | 3 | 7 |
| clk_1/inst/clk_out4 | initialize_audio/twi_controller/state_reg[2][0] | rightFir/firUnit_1/operativeUnit_1/rstn | 3 | 7 |
| clk_1/inst/clk_out4 | | initialize_audio/twi_controller/busFreeCnt0_2 | 3 | 7 |
| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[1] | | 3 | 8 |
| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/E[0] | | 2 | 8 |
| clk_1/inst/clk_out4 | initialize_audio/twi_controller/dataByte[7]_i_1_n_0 | | 3 | 8 |
| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/E[0] | | 1 | 8 |
| clk_1/inst/clk_out1 | | | 7 | 8 |
| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[1] | | 3 | 8 |
| clk_1/inst/clk_out1 | | rightFir/firUnit_1/operativeUnit_1/rstn | 5 | 10 |
| clk_1/inst/clk_out1 | dbuttons/cnt2 | dbuttons/cnt2[0]_i_1_n_0 | 4 | 13 |
| clk_1/inst/clk_out4 | | | 14 | 20 |
| clk_1/inst/clk_out4 | initialize_audio/initWord[30]_i_1_n_0 | | 6 | 23 |
| clk_1/inst/clk_out1 | audio_inout/D_R_O_int[23]_i_1_n_0 | rightFir/firUnit_1/operativeUnit_1/rstn | 7 | 24 |
| clk_1/inst/clk_out1 | audio_inout/D_L_O_int | rightFir/firUnit_1/operativeUnit_1/rstn | 6 | 24 |
| clk_1/inst/clk_out1 | audio_inout/Data_Out_int[31]_i_1_n_0 | | 12 | 25 |
| clk_1/inst/clk_out4 | | initialize_audio/delaycnt0 | 9 | 32 |
| clk_1/inst/clk_out1 | audio_inout/p_4_in | audio_inout/Data_In_int[31]_i_1_n_0 | 7 | 32 |
| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[0] | rightFir/firUnit_1/operativeUnit_1/rstn | 15 | 48 |
| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[0] | rightFir/firUnit_1/operativeUnit_1/rstn | 14 | 48 |
+----------------------+-----------------------------------------------------------+-----------------------------------------------+------------------+----------------+
File deleted
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
| Date : Tue Mar 7 15:54:33 2023
| Host : pc-elec-191 running 64-bit Ubuntu 20.04.5 LTS
| Command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
| Design : audioProc
| Device : xc7a200tsbg484-1
| Speed File : -1
| Design State : Synthesized
------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 22
+-----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
| CHECK-3 | Warning | Report rule limit reached | 1 |
| REQP-1839 | Warning | RAMB36 async control check | 20 |
+-----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
CHECK-3#1 Warning
Report rule limit reached
REQP-1839 rule limit reached: 20 violations have been found.
Related violations: <none>
REQP-1839#1 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[0] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[0]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#2 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[10] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[10]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#3 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[11] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[11]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#4 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[12] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[12]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#5 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[13] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[13]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#6 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[14] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[14]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#7 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[15] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[15]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#8 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[1] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[1]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#9 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[2] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[2]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#10 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[3] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[3]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#11 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[4] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[4]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#12 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[5] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[5]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#13 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[6] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[6]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#14 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[7] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[7]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#15 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[8] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[8]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#16 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[9] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[9]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#17 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRBWRADDR[12] (net: leftFir/firUnit_1/operativeUnit_1/bufferReadAddress[12]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferReadAddress_reg_rep[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#18 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRBWRADDR[13] (net: leftFir/firUnit_1/operativeUnit_1/bufferReadAddress[13]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferReadAddress_reg_rep[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#19 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRBWRADDR[14] (net: leftFir/firUnit_1/operativeUnit_1/bufferReadAddress[14]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferReadAddress_reg_rep[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#20 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRBWRADDR[15] (net: leftFir/firUnit_1/operativeUnit_1/bufferReadAddress[15]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferReadAddress_reg_rep[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
File deleted
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
| Date : Tue Mar 7 15:55:27 2023
| Host : pc-elec-191 running 64-bit Ubuntu 20.04.5 LTS
| Command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
| Design : audioProc
| Device : xc7a200tsbg484-1
| Speed File : -1
| Design State : Fully Routed
---------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 22
+-----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
| CHECK-3 | Warning | Report rule limit reached | 1 |
| REQP-1839 | Warning | RAMB36 async control check | 20 |
+-----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
CHECK-3#1 Warning
Report rule limit reached
REQP-1839 rule limit reached: 20 violations have been found.
Related violations: <none>
REQP-1839#1 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[0] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[0]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#2 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[10] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[10]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#3 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[11] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[11]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#4 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[12] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[12]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#5 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[13] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[13]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#6 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[14] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[14]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#7 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[15] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[15]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#8 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[1] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[1]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#9 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[2] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[2]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#10 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[3] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[3]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#11 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[4] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[4]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#12 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[5] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[5]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#13 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[6] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[6]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#14 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[7] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[7]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#15 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[8] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[8]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#16 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRARDADDR[9] (net: leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[9]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferWriteAddress_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#17 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRBWRADDR[12] (net: leftFir/firUnit_1/operativeUnit_1/bufferReadAddress[12]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferReadAddress_reg_rep[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#18 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRBWRADDR[13] (net: leftFir/firUnit_1/operativeUnit_1/bufferReadAddress[13]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferReadAddress_reg_rep[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#19 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRBWRADDR[14] (net: leftFir/firUnit_1/operativeUnit_1/bufferReadAddress[14]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferReadAddress_reg_rep[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
REQP-1839#20 Warning
RAMB36 async control check
The RAMB36E1 leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0 has an input control pin leftFir/firUnit_1/operativeUnit_1/soundBuffer_reg_0_0/ADDRBWRADDR[15] (net: leftFir/firUnit_1/operativeUnit_1/bufferReadAddress[15]) which is driven by a register (leftFir/firUnit_1/operativeUnit_1/bufferReadAddress_reg_rep[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>
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