@@ -73,6 +73,8 @@ The output signal `S_OUT` changes state at the same frequency as `S_IN`.
The digital filtering processor can be implemented with two modules, **an operative unit and a control unit** (described by a finite state automaton), both **provided incomplete**. These two combined modules reflect the previously described algorithm. Each operation corresponds to the execution of an instruction given by the automaton to the operative part (`loadShift`, `initAddress`, `incAddress`, `initSum`, `loadSum`, `loadOutput`). The operative part can send state information to the control automaton, such as a `processingDone` bit indicating that the last product $S(k − i) × H(i)$ will be processed during the next clock cycle.
**In this lab, we will implement a low-pass filter, with a sampling frequency of 48kHz, a cut-off frequency of 150Hz and 32 taps (coefficients).**
#### Architecture diagram of the filtering unit:

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@@ -182,7 +184,7 @@ To do so, select `operativeUnit.vhd` and right-click to select *Disable File*. T
The expected sequence at the output of the filter is (in the form of signed integers):