udpate filter to be up-to-date with 32 coefficients!

docs/vhdl/filter.md

@@ -73,6 +73,8 @@ The output signal `S_OUT` changes state at the same frequency as `S_IN`.
 
 The digital filtering processor can be implemented with two modules, **an operative unit and a control unit** (described by a finite state automaton), both **provided incomplete**. These two combined modules reflect the previously described algorithm. Each operation corresponds to the execution of an instruction given by the automaton to the operative part (`loadShift`, `initAddress`, `incAddress`, `initSum`, `loadSum`, `loadOutput`). The operative part can send state information to the control automaton, such as a `processingDone` bit indicating that the last product $S(k − i) × H(i)$ will be processed during the next clock cycle.
 
+**In this lab, we will implement a low-pass filter, with a sampling frequency of 48kHz, a cut-off frequency of 150Hz and 32 taps (coefficients).**
+
 #### Architecture diagram of the filtering unit:
 
 ![Fir Unit Architecture](../img/filtre/firUnit.png#center#shadow)
@@ -182,7 +184,7 @@ To do so, select `operativeUnit.vhd` and right-click to select *Disable File*. T
 
 The expected sequence at the output of the filter is (in the form of signed integers):
 
-**317,476,925,1589,2354,3087,3661,3975,3975,3661,3087,2354,1589,925,476,317,0,0,0,0,1,2,3,4,4,5,2,-1,-5,-10,-16,-23,-30,-37,-43,-49,-56,-61,-64,-68,-68, -70**
+**154,173,227,315,433,576,739,915,1097,1276,1447,1602,1734,1838,1910,1947,1947,1910,1838,1734,1602,1447,1276,1097,915,739,576,433,315,227,173,154,0,0,1,0,0,1,0,1,1,0,0,-1,-2,-3,-5,-7,-9,-12,-15,-19,-23,-27,-31,-35,-39,-43,-47,-51,-54,-57,-60,-62,-64,-66,-67,-68,-69,-69,-69,-70...**
 
 Simulate the testbench associated with the file tb_firUnit.vhd.