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Commit 6307e576 authored by ARZEL Matthieu's avatar ARZEL Matthieu
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Mise à jour de TP filtre

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......@@ -15,6 +15,11 @@ If no repository creation is planned for your course, or if you want to do this
This lab offers a brief introduction to the design of digital integrated circuits, by discovering the integration of an essential function in information and signal processing: filtering. Starting from an algorithm, you will have to describe an architecture in VHDL (a language dedicated to electronics), perform its synthesis and finally test this architecture on a reconfigurable Field-Programmable Gate Array (FPGA) circuit.
!!! warning "Be aware that it is a simple/simplified architecture"
Many architectures of filters exist, depending on the filter types and the application constraints (accuracy, stability, processing throughput, latency, power consumption, etc.).
The solution proposed here is a very simple one, with no optimization of the processing or of the quantization.
It aims at giving a first view on designing digital circuits for signal processing.
!!! note
A VHDL code will be partially proposed to you, you will have to complete it, based on the preparatory work requested.
......@@ -25,7 +30,7 @@ This lab offers a brief introduction to the design of digital integrated circuit
### Description of the algorithm
A sound signal s(t), continuous in time and value, is commonly sampled at 44.1kHz for musical applications (22kHz for radio and 8kHz for the telephone) and then digitized on a limited number of bits (8, 16 or 24 bits are common). The result is then a sequence of samples $S(k)$. This signal can be filtered for many reasons, such as to accentuate certain effects or correct imperfections for example. In this lab, we will only consider simple linear filters with Finite Impulse Response (FIR). Applying such a filter h to a continuous signal $s(t)$ would require an analog filter circuit capable of performing the convolution $h \times s(t)$. To perform it on a digital signal, we will unroll an equivalent calculation, replacing the integral of the convolution with a discrete sum over a finite depth of N samples and keeping the multiplication of the convolution. Thus, for any sample $S(k)$, the filtered sample $S'(k)$ is such that:
A sound signal s(t), continuous in time and value, is commonly sampled at 44.1kHz (or 48kHz) for musical applications (22kHz for radio and 8kHz for the telephone) and then digitized on a limited number of bits (8, 16 or 24 bits are common). The result is then a sequence of samples $S(k)$. This signal can be filtered for many reasons, such as to accentuate certain effects or correct imperfections for example. In this lab, we will only consider simple linear filters with Finite Impulse Response (FIR). Applying such a filter h to a continuous signal $s(t)$ would require an analog filter circuit capable of performing the convolution $h \times s(t)$. To perform it on a digital signal, we will unroll an equivalent calculation, replacing the integral of the convolution with a discrete sum over a finite depth of N samples and keeping the multiplication of the convolution. Thus, for any sample $S(k)$, the filtered sample $S'(k)$ is such that:
$$
S'(k) = \sum_{i=0}^{N-1}S(k-i) \times H(i)
......@@ -66,14 +71,14 @@ The output signal `S_OUT` changes state at the same frequency as `S_IN`.
### Description of the circuit architecture
The digital filtering processor can be implemented with two modules, **an operative unit and a control unit** (described by a finite state automaton), both **provided incomplete**. These two combined modules reflect the previously described algorithm. Each operation corresponds to the execution of an instruction given by the automaton to the operative part (`loadShift`, `initAddress`, `incAddress`, `initSum`, `loadSum`, `loadOutput`). The operative part can send state information to the control automaton, such as a `processingDone` bit indicating that the last product $S(k − i) × H(i)$ is being processed.
The digital filtering processor can be implemented with two modules, **an operative unit and a control unit** (described by a finite state automaton), both **provided incomplete**. These two combined modules reflect the previously described algorithm. Each operation corresponds to the execution of an instruction given by the automaton to the operative part (`loadShift`, `initAddress`, `incAddress`, `initSum`, `loadSum`, `loadOutput`). The operative part can send state information to the control automaton, such as a `processingDone` bit indicating that the last product $S(k − i) × H(i)$ will be processed during the next clock cycle.
#### Architecture diagram of the filtering unit:
![Fir Unit Architecture](../img/filtre/firUnit.png#center#shadow)
!!! note
Corresponds to the VHDL file `FirUnit.vhd` that to eventually be completed
Corresponds to the VHDL file `FirUnit.vhd` that you have in your project.
#### Finite state machine diagram:
......@@ -100,13 +105,14 @@ The digital filtering processor can be implemented with two modules, **an operat
#### Work in the classroom
You will use the Xilinx Vivado software to describe and synthesize your circuit based on the files available on the Moodle platform of the UV Électronique, Travaux Pratiques section. During the two sessions, ***you will complete the provided code of the control and operative parts, then you will test the result of your reflection at each session and deposit on the moodle repository of your room the VHDL files that you will have edited.*** To validate the effect of the filter, you can test its quantization noise reduction efficiency through different configurations explained in class.
You will use the Xilinx Vivado software to describe and synthesize your circuit based on the files available in your VIVADO project. During the two sessions, ***you will complete the provided code of the control and operative parts, then you will test the result of your implementation at each session and commit, with GIT, the VHDL files that you will have edited.*** To validate the effect of the filter, you can test its quantization noise reduction efficiency through different configurations explained in class.
The circuit to be configured is a Xilinx Artix 7 FPGA which is integrated on the Digilent Nexys Video board shown in figure 2.2.4 and including, in addition to the FPGA, many peripherals.
The circuit to be configured is a Xilinx Artix 7 FPGA which is integrated on the Digilent Nexys Video board.
The documentation of the board is available [here](https://digilent.com/reference/programmable-logic/nexys-video/reference-manual).
The documentation of the board is available on the Moodle page of the UV Électronique. This documentation is *useful* to understand the use of the peripherals.
This documentation is *useful* to understand the use of the peripherals.
![Atlys board](../img/filtre/Atlys.png#center#shadow)
![Atlys board](../img/filtre/Nexysvideo.png#center#shadow)
## From description to control unit test
......@@ -132,7 +138,7 @@ cd !$
Remember to adapt the link of the command below according to the repository on gitlab
```bash
git clone https://gitlab-df.imt-atlantique.fr/tp-vhdl-mee/medcon/gr-vhdl-$USER/tp-filtre-etudiant-$USER.git
git clone https://gitlab-df.imt-atlantique.fr/tp-vhdl-mee/UE-name/gr-vhdl-$USER/tp-filtre-etudiant-$USER.git
```
The `git clone` command allows you to retrieve the entire `git` repository with its history of modifications.
......@@ -152,7 +158,7 @@ include-markdown "vhdl/launch-vivado.md"
A TCL script is provided to automate the project creation. To use it, you need to:
- go to the Tcl console of Vivado, at the bottom of the window.
- go to the `Projet` directory with the `cd` command: `cd tp-filtre-etudiant-$USER/proj` (here you have to manually replace `$USER` with your login)
- go to the `Project` directory with the `cd` command: `cd tp-filtre-etudiant-$USER/proj` (here you have to manually replace `$USER` with your login)
- type the command `source ./create_project.tcl`
......@@ -171,11 +177,12 @@ You must replace in the file `controlUnit.vhd` the parts `_BLANK_` with the appr
### Simulation
A "compiled" operative unit is available to simulate and test your description of the control part. Your project must therefore at this stage contain the file `operativeUnitIP.v` instead of the file `operativeUnit.vhd` that you will soon modify...
A "compiled" operative unit is available to simulate and test your description of the control part. Your project must therefore at this stage contain the file `operativeUnit.v` instead of the file `operativeUnit.vhd` that you will soon modify...
To do so, select `operativeUnit.vhd` and right-click to select *Disable File*. Then, `operativeUnit.v` should replace it in the circuit hierarchy.
The expected sequence at the output of the filter is (in the form of signed integers):
**0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8 -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116.**
**317,476,925,1589,2354,3087,3661,3975,3975,3661,3087,2354,1589,925,476,317,0,0,0,0,1,2,3,4,4,5,2,-1,-5,-10,-16,-23,-30,-37,-43,-49,-56,-61,-64,-68,-68, -70**
Simulate the testbench associated with the file tb_firUnit.vhd.
......@@ -186,12 +193,13 @@ Simulate the testbench associated with the file tb_firUnit.vhd.
Run the design flow until the bitstream is produced and transfer it to Moodle in the repository provided for your room. It can then be tested on the available board connected to the *PC prof*. The *Line-in* input can be connected to any analog source via a 3.5mm jack (output from a smartphone or a PC audio card) and the *Line-out* output must be connected to a headset or an audio amplifier.
The *Nexys VIDEO* board is configured so that the 5 switches `SW7` to `SW3` at the bottom left and the central button `BTNC` at the bottom right are used.
The *Nexys VIDEO* board is configured so that the 5 switches `SW7` to `SW2` at the bottom left and the central button `BTNC` at the bottom right are used.
When the user presses the *BTNC* button, he can listen to the original audio stream coded on 24 bits and not filtered, otherwise he listens to the audio stream under-quantified at best on 8 bits at the input or output of the filter. The *SW7* switch precisely controls this selection. When *SW7=ON*, the user listens to the filter output, otherwise he listens to the input under-quantified by the filter on 8 bits at best.
When the user presses the *BTNC* button, he can listen to the original audio stream coded on 24 bits and not filtered, otherwise he listens to the audio stream under-quantized at best on 16 bits at the input or output of the filter. The *SW7* switch precisely controls this selection. When *SW7=ON*, the user listens to the filter output, otherwise he listens to the input under-quantized by the filter on 16 bits at best.
Under-quantization is managed by the combination of switches *SW6* to *SW3*. The number of bits removed from the 8 at the input of the filter is coded in natural binary by *MSB=SW5 SW4 LSB=SW3* and *SW6* allows to select the type of rounding (if *ON*, to the nearest, otherwise by truncation).
Under-quantization is managed by the combination of switches *SW6* to *SW2*. The number of bits removed from the 16 at the input of the filter is coded in natural binary by *MSB=SW5 SW4 SW3 LSB=SW2* and *SW6* allows to select the type of rounding (if *ON*, to the nearest, otherwise by truncation).
For instance, it you want to remove 10 bits, then *SW5 = ON | SW4=OFF | SW3 = ON | SW2 = OFF*.
!!! question "Question filter 3 (answer to be completed in the file `docs/compte-rendu.md`)"
......@@ -201,7 +209,7 @@ Under-quantization is managed by the combination of switches *SW6* to *SW3*. The
### VHDL description
You must remove the file `operativeUnitIP.v` and add the file `operativelUnit.vhd` to the project. Replace the parts `_BLANK_` with the appropriate VHDL code respecting the [Operative Unit architecture](#architecture-diagram-of-the-operative-unit)
You must remove the file `operativeUnit.v` and add the file `operativelUnit.vhd` to the project. Replace the parts `_BLANK_` with the appropriate VHDL code respecting the [Operative Unit architecture](#architecture-diagram-of-the-operative-unit)
!!! question "Question 4 (answer to be completed in the file `docs/compte-rendu.md`)"
How many processes are used and what are their natures?
......@@ -209,7 +217,7 @@ You must remove the file `operativeUnitIP.v` and add the file `operativelUnit.vh
### Simulation
Your project must now contain the file `operativeUnit.vhd` instead of the file `operativeUnitIP.v`. Then simulate the testbench associated with the file `tb_firUnit.vhd`.
Your project must now contain the file `operativeUnit.vhd` instead of the file `operativeUnit.v`. Then simulate the testbench associated with the file `tb_firUnit.vhd`.
!!! question "Question filter 5 (answer to be completed in the file `docs/compte-rendu.md`)"
Does the simulation allow you to validate your VHDL description? If not, what is the problem? How can you fix it? Justify
......
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