@@ -8,13 +8,28 @@ Your mission is to wire correctly all the building blocks of a digital synthesiz
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@@ -8,13 +8,28 @@ Your mission is to wire correctly all the building blocks of a digital synthesiz
The digital processing core is a reconfigurable Field-Programmable Gate Array (FPGA), an Artix 7 by AMD, associated to peripherals on a board, the Digilent Nexys Video board, as illustrated on the figure below
The digital processing core is a reconfigurable Field-Programmable Gate Array (FPGA), an Artix 7 by AMD, associated to peripherals on a board, the Digilent Nexys Video board, as illustrated on the figure below
This lab offers a brief introduction to the design of digital integrated circuits with simple blocks to analyse and then to interconnect.
This lab offers a brief introduction to the design of digital integrated circuits with **simple blocks to analyse and then to interconnect**.
Once wired, all the blocks process samples so that tones can be generated with orders coming from a USB keyboard.
Once wired, all the blocks process samples so that tones can be generated with orders coming from a USB keyboard.
Starting from blocks described in VHDL (a language dedicated to electronics), you will have to
!!! note "Remember this when you will analyse the blocks!"
1. analyse time diagrams of blocks to deduce their functions,
The basic blocks that you will use are similar to those seen in the tutorials ("TD"):
2. wire all the blocks together, by completing a VHDL file (wave_generator.vhd), based on your analysis of the time diagrams,
- logic gates,
- decoders,
- arithmetic operator,
- up/down counter,
- register,
- multiplexeur,
- memory (a table of values that you read at an adress given as input).
Starting from *modules* (that is the term used in VHDL to design a block with input and outpput ports) described in VHDL (a language dedicated to electronics), you will have to
1. analyse time diagrams of modules (i.e. blocks) to deduce their functions (you can also read the VHDL code to infer these functions)
2. wire all the modules together, by completing a VHDL file (wave_generator.vhd), based on your analysis of the time diagrams,
3. perform its synthesis,
3. perform its synthesis,
4. test the resulting circuit on an FPGA by playing some tones.
4. test the resulting circuit on an FPGA by playing some tones.
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@@ -58,7 +73,7 @@ A git repository has been created for each student on the school's DFVS gitlab i
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@@ -58,7 +73,7 @@ A git repository has been created for each student on the school's DFVS gitlab i
First, open a terminal: ++ctrl+alt+t++
First, open a terminal: ++ctrl+alt+t++
- Create a directory for the UE Électronique and move into it:
- Create a directory for the UE Electrical Engineering and move into it:
!!! warning
!!! warning
Remember to adapt the path of the command below to your own needs
Remember to adapt the path of the command below to your own needs
