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Commit ecffc42d authored by BAZIN Jean-Noel's avatar BAZIN Jean-Noel
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library IEEE;
use ieee.std_logic_1164.all;
entity OUEX is
port (I_A : in std_logic;
I_B : in std_logic;
O_S : out std_logic
);
end OUEX;
architecture LOGIC_EQ of OUEX is
begin
-- To be completed
end LOGIC_EQ;
architecture DIRECT_TRUTH_TABLE of OUEX is
begin
-- To be completed
end DIRECT_TRUTH_TABLE;
architecture PROCESS_TRUTH_TABLE of OUEX is
begin
-- To be completed
end PROCESS_TRUTH_TABLE;
library IEEE;
use ieee.std_logic_1164.all;
entity tb_OUEX is end;
architecture ARCHI of tb_OUEX is
signal A, B, S1, S2, S3 : std_logic;
begin
DUT1 : entity work.OUEX(LOGIC_EQ)
port map (
I_A => A,
I_B => B,
O_S => S1
);
DUT2 : entity work.OUEX(DIRECT_TRUTH_TABLE)
port map (
I_A => A,
I_B => B,
O_S => S2
);
DUT3 : entity work.OUEX(PROCESS_TRUTH_TABLE)
port map (
I_A => A,
I_B => B,
O_S => S2
);
A <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
B <= '0', '1' after 20 ns;
end ARCHI;
library IEEE;
use ieee.std_logic_1164.all;
entity D_flip_flop is
port (I_Clk : in std_logic;
I_Reset : in std_logic;
I_D : in std_logic;
O_Q : out std_logic
);
end D_flip_flop;
architecture Behavioral of D_flip_flop is
begin
Init : process (I_Reset)
begin
if I_Reset = '1' then
O_Q <= '0';
end if;
end process Init;
Sync : process (I_Clk)
begin
if rising_edge(I_Clk) and I_Reset = '0' then
O_Q <= I_D;
end if;
end process Sync;
end Behavioral;
library IEEE;
use ieee.std_logic_1164.all;
entity tb_D_flip_flop is end;
architecture ARCHI of tb_D_flip_flop is
signal CK : std_logic := '0';
signal R, D, Q : std_logic;
begin
DUT : entity work.D_flip_flop(Behavioral)
port map (
I_Clk => CK,
I_Reset => R,
I_D => D,
O_Q => Q
);
CK <= not CK after 10 ns;
R <= '0', '1' after 2 ns, '0' after 15 ns;
D <= '1', '0' after 35 ns, '1' after 55 ns;
end ARCHI;
library IEEE;
use ieee.std_logic_1164.all;
entity Decoder is
port (
I_0 : in std_logic;
I_1 : in std_logic;
I_2 : in std_logic;
O_out : out std_logic_vector (7 downto 0)
);
end Decoder;
architecture Behavioral of Decoder is
begin
process (I_2, I_0)
begin
if I_2 = '0' and I_1 = '0' and I_0 = '0' then
O_out <= "00000001";
elsif I_2 = '0' and I_1 = '0' and I_0 = '1' then
O_out <= "00000010";
elsif I_2 = '0' and I_1 = '1' and I_0 = '0' then
O_out <= "00000100";
elsif I_2 = '0' and I_1 = '1' and I_0 = '1' then
O_out <= "00001000";
elsif I_2 = '1' and I_1 = '0' and I_0 = '0' then
O_out <= "00010000";
elsif I_2 = '1' and I_1 = '0' and I_0 = '1' then
O_out <= "00100000";
elsif I_2 = '1' and I_1 = '1' and I_0 = '0' then
O_out <= "01000000";
elsif I_2 = '1' and I_1 = '1' and I_0 = '1' then
O_out <= "10000000";
else O_out <= "00000000";
end if;
end process;
end Behavioral;
library IEEE;
use ieee.std_logic_1164.all;
entity tb_Decoder is end;
architecture ARCHI of tb_Decoder is
signal I2, I1, I0 : std_logic;
signal IN_VECT : std_logic_vector(2 downto 0);
signal DEC_OUT : std_logic_vector(7 downto 0);
begin
DUT : entity work.Decoder(Behavioral)
port map (I_0 => I2,
I_1 => I1,
I_2 => I0,
O_out => DEC_OUT
);
I2 <= IN_VECT(2);
I1 <= IN_VECT(1);
I0 <= IN_VECT(0);
IN_VECT <= "101", "110" after 10 ns, "000" after 20 ns, "010" after 30 ns,
"100" after 40 ns, "010" after 50 ns, "001" after 60 ns, "011" after 70 ns,
"101" after 80 ns, "110" after 90 ns, "100" after 100 ns;
end ARCHI;
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Counter1 is
generic (
N : integer := 10
);
port (
I_Clock : in std_logic;
I_Reset : in std_logic;
O_Count : out std_logic_vector (4 downto 0)
);
end entity Counter1;
architecture Behavioral of Counter1 is
signal S_Counter : integer range 0 to N-1; -- counting signal
begin
process (I_Clock, I_Reset)
begin
if (I_Reset = '0') then -- initialization
S_Counter <= 0;
O_Count <= (others => '0');
elsif rising_edge(I_Clock) then -- or “if I_Clock’EVENT and I_Clock =’1’” clock rising edge
if (S_Counter = 0) then
S_Counter <= N-1; -- set counter value to N-1
else
S_Counter <= S_Counter -1; -- increment counting signal
end if;
O_Count <= std_logic_vector(to_unsigned (S_Counter, 5));
end if;
end process;
end Behavioral;
library IEEE;
use ieee.std_logic_1164.all;
entity tb_Counter is end;
architecture ARCHI of tb_Counter is
component Counter1 is
generic (
N : integer := 10
);
port (
I_Clock : in std_logic;
I_Reset : in std_logic;
O_Count : out std_logic_vector (4 downto 0)
);
end component;
signal CK, R : std_logic := '0';
signal COUNT : std_logic_vector(4 downto 0) := "00000";
begin
DUT : Counter1
generic map (
N => 12
)
port map (
I_Clock => CK,
I_Reset => R,
O_Count => COUNT
);
CK <= not CK after 10 ns;
R <= '0', '1' after 5 ns;
end ARCHI;
library IEEE;
use ieee.std_logic_1164.all;
entity Operator is
port (
I_0 : in std_logic;
I_1 : in std_logic;
I_2 : in std_logic;
O_out : out std_logic_vector (7 downto 0)
);
end Operator;
architecture Behavioral of Operator is
begin
process (I_0, I_1, I_2)
begin
if I_2 = '0' and I_1 = '0' and I_0 = '0' then
O_out <= "00000001";
elsif I_2 = '0' and I_1 = '0' and I_0 = '1' then
O_out <= "00000010";
elsif I_2 = '0' and I_1 = '1' and I_0 = '0' then
O_out <= "00000100";
elsif I_2 = '0' and I_1 = '1' and I_0 = '1' then
O_out <= "00001000";
elsif I_2 = '1' and I_1 = '0' and I_0 = '0' then
O_out <= "00010000";
elsif I_2 = '1' and I_1 = '0' and I_0 = '1' then
O_out <= "00100000";
elsif I_2 = '1' and I_1 = '1' and I_0 = '0' then
O_out <= "01000000";
end if;
end process;
end Behavioral;
library IEEE;
use ieee.std_logic_1164.all;
entity tb_Operator is end;
architecture ARCHI of tb_Operator is
signal I0, I1, I2 : std_logic;
signal IN_VECT : std_logic_vector(2 downto 0);
signal DEC_OUT : std_logic_vector(7 downto 0);
begin
DUT : entity work.Operator(Behavioral)
port map (
I_0 => I0,
I_1 => I1,
I_2 => I2,
O_out => DEC_OUT
);
I0 <= IN_VECT(0);
I1 <= IN_VECT(1);
I2 <= IN_VECT(2);
IN_VECT <= "101", "110" after 10 ns, "000" after 20 ns, "010" after 30 ns,
"100" after 40 ns, "010" after 50 ns, "001" after 60 ns, "011" after 70 ns,
"101" after 80 ns, "100" after 90 ns, "110" after 100 ns;
end ARCHI;
----------------------------------------------
-- INTEGER adder
----------------------------------------------
entity ADDER1 is
port (
A : in integer;
B : in integer;
S : out integer
);
end ADDER1;
architecture Behavioral of ADDER1 is
begin
S <= A + B;
end Behavioral;
----------------------------------------------
-- SIGNED adder2
----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ADDER2 is
port (
A : in signed(7 downto 0);
B : in signed(7 downto 0);
S : out signed(7 downto 0)
);
end ADDER2;
architecture Behavioral of ADDER2 is
begin
S <= A + B;
end Behavioral;
----------------------------------------------
-- Testbench for ADDER1 and ADDER2
----------------------------------------------
entity tb_ADDER is end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
architecture ARCHI1 of tb_ADDER is
signal INT_A, INT_B, INT_S : integer;
signal SIGN_A, SIGN_B, SIGN_S : signed(7 downto 0);
begin
DUT1 : entity work.ADDER1(Behavioral)
port map (
A => INT_A,
B => INT_B,
S => INT_S
);
DUT2 : entity work.ADDER2(Behavioral)
port map (
A => SIGN_A,
B => SIGN_B,
S => SIGN_S
);
INT_A <= 0, -5 after 10 ns, 22 after 20 ns, -8 after 30 ns;
INT_B <= 100, 15 after 5 ns, -3 after 15 ns, 9 after 25 ns;
SIGN_A <= to_signed(INT_A, 8);
SIGN_B <= to_signed(INT_B, 8);
end ARCHI1;
library IEEE;
use ieee.std_logic_1164.all;
entity Counter2 is
generic (
N : integer := 10
);
port (
I_Clock : in std_logic;
I_Reset : in std_logic;
O_Detect : out std_logic
);
end entity Counter2;
architecture Behavioral of Counter2 is
signal S_Counter : integer; -- counting signal
begin
process (I_Clock, I_Reset)
begin
if (I_Reset = '0') then -- initialization
S_Counter <= 0;
elsif rising_edge(I_Clock) then -- or “if I_Clock’EVENT and I_Clock =’1’” clock rising edge
if (S_Counter = N-1) then
S_Counter <= 0; -- reset counter value at 0
else
S_Counter <= S_Counter + 1; -- increment counting signal
end if;
end if;
end process;
O_Detect <= '1' when (S_Counter = N-1) else '0';
end Behavioral;
library IEEE;
use ieee.std_logic_1164.all;
entity tb_Counter2 is end;
architecture ARCHI of tb_Counter2 is
signal CK, R, DETECT : std_logic := '0';
begin
DUT : entity work.Counter2(Behavioral)
generic map(
N => 10
)
port map (
I_Clock => CK,
I_Reset => R,
O_Detect => DETECT
);
CK <= not CK after 10 ns;
R <= '0', '1' after 5 ns;
end ARCHI;
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