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Commit da1c8679 authored by ARZEL Matthieu's avatar ARZEL Matthieu
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new clock @48kHz

parent 652a0d85
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......@@ -218,7 +218,7 @@ module audioProc(
reg[3:0] lrclkcnt=0;
always@(posedge(clk_out_100MHZ))begin
if (lrclkcnt==15)begin
if (lrclkcnt==8)begin
pulse48kHz<=1;
lrclkcnt<=0;
end
......@@ -230,6 +230,23 @@ module audioProc(
// Synthe
// Marz
/////////////////////////////
// Clock @48kHz derived from the 12MHz clock
reg clock48kHz;
reg[7:0] cnt=0;
always@(posedge(ac_mclk))begin
if (cnt==124)begin
clock48kHz<=1;
cnt <= cnt+1;
end
else if (cnt==249)begin
clock48kHz<=0;
cnt<=0;
end
else
cnt <= cnt+1;
end
wire [23:0] inputLeftSample, inputRightSample,outputLeftSample,outputRightSample;
wire [4:0] configSw;
wire [1:0] waveSw;
......@@ -256,7 +273,7 @@ module audioProc(
synthesizer synthe
(
pulse48kHz, // : in std_logic;
clock48kHz, // : in std_logic;
rst,// : in std_logic;
waveSw[1:0],
configSw[3:0],
......
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