There are instructions in VHDL that are not synthesizable, they are not intended to be used to describe an electronic circuit. The usefulness of these instructions is that they facilitate simulations and the rapid creation of golden models (functional reference model for comparison with the circuit that we want to design).
## Text file manipulation
To simulate a circuit it is sometimes very useful to be able to manipulate text files in a test bench or even in a circuit (before synthesis).
We can use a text file to :
- store values to be applied to inputs
- store expected internal or output values and compare them to the values present at the output of the circuit
- initialize RAM content of a circuit on FPGA
Input text file content:
```
12 13
15 14
11 2
1234 678
345 234
12 987
-12 -87
-3124 9786
```
```.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all;
entity testStdLogicTextio is
end entity testStdLogicTextio;
architecture arch of testStdLogicTextio is
file F_input : text open read_mode is "../input.txt";
file F_output : text open write_mode is "../output.txt";
signal SR_Clock : std_logic := '0';
signal SR_reset : std_logic;
signal SR_Value1 : integer;
signal SR_Value2 : integer;
signal SR_Value3 : integer;
signal SR_Value4 : integer;
signal SR_reading : std_logic;
begin
SR_reset <= '1', '0' after 3 ns;
SR_Clock <= not SR_Clock after 10 ns;
process (SR_Clock, SR_reset) is
variable theline : line;
variable V_Value1 : integer;
variable V_Value2 : integer;
begin
if(SR_reset = '1')then
SR_Value1 <= 0;
SR_Value2 <= 0;
SR_reading <= '0';
elsif rising_edge(SR_Clock) then
if(not endfile(F_input))then
readline(F_input, theline);
read(theline, V_Value1);
SR_Value1 <= V_Value1;
read(theline, V_Value2);
SR_Value2 <= V_Value2;
SR_reading <= '1';
else
SR_reading <= '0';
end if;
end if;
end process;
SR_Value3 <= SR_Value1*SR_Value2;
SR_Value4 <= SR_Value2+SR_Value1;
process (SR_Clock, SR_reset) is
variable theline : line;
begin
if SR_reset = '1' then
elsif rising_edge(SR_Clock) then
if(SR_reading = '1')then
write(theline, string'("Op1 = "));
write(theline, SR_Value1, left, 8); --alignement a gauche, taille minimum de 8 caracteres
write(theline, string'("Op2 = "));
write(theline, SR_Value2, left, 8); --alignement a gauche, taille minimum de 8 caracteres
write(theline, string'("ResMult = "));
write(theline, SR_Value3, right, 4); --alignement a droite, taille minimum de 4 caracteres
write(theline, string'(" ResAdd = "));
write(theline, SR_Value4, left, 9); --alignement a gauche, taille minimum de 9 caracteres
writeline(F_output, theline);
-- les deux lignes ci-dessous sont expliquees dans la section suivante
