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Commit b19b630a authored by BAZIN Jean-Noel's avatar BAZIN Jean-Noel
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add VHDL conditional structure page

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# Conditionnal structures
## `if`, `elsif`, `else`
This kind of conditionnal structure is always inside an explicit process :
```.vhdl
signal A : std_logic_vector(2 downto 0);
signal S : std_logic_vector(2 downto 0);
--
process(A)
begin
if (A = "000") then
S <= "000";
elsif (A = "001") then
S <= "001";
elsif (A = "001") then
S <= "011";
elsif (A = "010") then
S <= "011";
elsif (A = "011") then
S <= "010";
elsif (A = "100") then
S <= "110";
elsif (A = "101") then
S <= "111";
elsif (A = "110") then
S <= "110";
elsif (A = "111") then
S <= "100";
else
S<="000";
end if;
end process;
```
!!! warning
Never forget the `else` at the end when in a combinatorial process
## `case`
This kind of conditionnal structure is always inside an explicit process as well :
```.vhdl
Process(A)
Begin
Case A is
when "000" => S <= "000";
when "001" => S <= "001";
when "001" => S <= "011";
when "010" => S <= "011";
when "011" => S <= "010";
when "100" => S <= "110";
when "101" => S <= "111";
when "110" => S <= "110";
when "111" => S <= "100";
when others => S <= "000";
end case;
end process ;
```
!!! warning
Never forget the `when others` at the end when in a combinatorial process
## Conditionnal assignment `when` `else`
This kind of conditionnal structure is described as implicit process :
```.vhdl
S <= "000" when(A = "000")else
"001" when(A = "001")else
"011" when(A = "010")else
"010" when(A = "011")else
"110" when(A = "100")else
"111" when(A = "101")else
"110" when(A = "110")else
"100" when(A = "111")else
"000";
```
This type of assignment is very convenient and readable for the assignment of a binary signal.
```.vhdl
W <= '1' when(A = "01110" or B = '1' and C = '1')else '0';
```
!!! warning
Never forget the `else` at the end.
## Conditionnal assignment `with` `select`
```.vhdl
with A select S <=
"000" when "000",
"001" when "001",
"011" when "010",
"010" when "011",
"110" when "100",
"111" when "101",
"110" when "110",
"100" when "111",
"000" when others;
```
!!! warning
Never forget the `when others` at the end.
docs/memo/index.md
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......@@ -3,7 +3,7 @@
An integrated circuit is designed from its description in terms of logical operators, taken from a library, linked by connections or equipotentials. This description is called the netlist. This netlist can be obtained either from a schematic or from a description in a high level language, for example VHDL.
The role of an electronic circuit is to process electrical signals present on its inputs and to generate coherent signals on its outputs according to the specifications. The signal is the central object of the VHDL language:
- its declaration is infered in synthesis by an equipotential ;
- its declaration is infered in synthesis by an equipotential
- its state is defined by the assignment symbol (connection in the electronic sense) `<=`. e.g.: `C <= A and B;` (C receives A and B) will be synthesized by :
......
docs/memo/process.md
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## Process
# Process
Processes in VHDL are used to describe the operation of a part of a circuit, in particular circuits (using a clock) or complex combinatorial circuits. In processes it is possible to use conditional structures such as the classic if/elsif/else and case.
......@@ -7,7 +7,7 @@ A process has a sensitivity list, i.e. a list of input signals. The process reac
On the other hand, a signal that is only updated in the process does not need to be present in the sensitivity list.
### Synchronous process
## Synchronous process
A synchronous process has, as its name indicates, an operation synchronized by the events affecting a signal in its sensitivity list. We call this signal the clock, and most often processes of this type are synchronized on the rising edge of the clock, i.e. the passage from state 0 to state 1. The process updates the signals that it controls only at the time of the rising edge, whatever the evolution of the signals used in this process. For this reason, the sensitivity list of a synchronous process is a bit special. It contains only the clock and possibly a reset in the case of an asynchronous reset. Even if signals are read or used in the synchronous part, it is not necessary to put them in the sensitivity list.
......@@ -30,7 +30,7 @@ end process;
A really good overview of the question is presented here *Get your Priorities Right — Make your Design Up to 50% Smaller* [https://www.xilinx.com/support/documentation/white_papers/wp275.pdf](../files/wp275.pdf)
### Asynchronous process
## Asynchronous process
The asynchronous process, being by definition combinatorial, must react immediately to the change of state of any of its input signals.
It is therefore imperative to fill in the sensitivity list exhaustively.
......@@ -50,7 +50,7 @@ begin
end process;
```
### Implicit process
## Implicit process
It is possible to describe the operation of a circuit outside an explicit process.
This is called an implicit process. Implicit processes are used when it is not necessary to use a process as such. Putting a permanent connection (assignment) between two signals in an explicit process is of no interest, it is done outside:
......
docs/memo/synthesizable-vhdl.md
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# Examples of synthesizable VHDL
The examples presented in this document are all inferred on the dedicated resources of FPGA (adder, counter, RAM...). They are synthesizable VHDL codes that can be used to describe a circuit that we want to implement on FPGA or ASIC.
The examples presented here are all inferred on the dedicated resources of FPGA (adder, counter, RAM...). They are synthesizable VHDL codes that can be used to describe a circuit that we want to implement on FPGA or ASIC.
## Process
Processes in VHDL are used to describe the operation of a part of a circuit, in particular circuits (using a clock) or complex combinatorial circuits. In processes it is possible to use conditional structures such as the classic if/elsif/else and case.
A process has a sensitivity list, i.e. a list of input signals. The process reacts to the changes of state of the signals that are present in the sensitivity list. It is crucial to fill in this sensitivity list correctly.
On the other hand, a signal that is only updated in the process does not need to be present in the sensitivity list.
### Synchronous process
A synchronous process has, as its name indicates, an operation synchronized by the events affecting a signal in its sensitivity list. We call this signal the clock, and most often processes of this type are synchronized on the rising edge of the clock, i.e. the passage from state 0 to state 1. The process updates the signals that it controls only at the time of the rising edge, whatever the evolution of the signals used in this process. For this reason, the sensitivity list of a synchronous process is a bit special. It contains only the clock and possibly a reset in the case of an asynchronous reset. Even if signals are read or used in the synchronous part, it is not necessary to put them in the sensitivity list.
```.vhdl
process(I_Clock) -- sensitivity list in brackets, consisting of a clock and eventually a reset
begin
if(rising_edge(I_Clock)) then
if I_Reset = '1' then -- active high synchronous reset
-- what happens if the reset is active
else
-- what happens at the time of a clock rising edge without reset
end if;
end if;
end process;
```
!!! question "Is the asynchronous reset mandatory ?"
The asynchronous reset is often present in VHDL synchronous process. But in some if not most FPGA designs, it is vastly optionnal. Its presence might even be a nuisance.
A really good overview of the question is presented here *Get your Priorities Right — Make your Design Up to 50% Smaller* [https://www.xilinx.com/support/documentation/white_papers/wp275.pdf](../files/wp275.pdf)
### Asynchronous process
The asynchronous process, being by definition combinatorial, must react immediately to the change of state of any of its input signals.
It is therefore imperative to fill in the sensitivity list exhaustively.
```.vhdl
process(S1,S2,S3,S3,S5,S6)
begin
-- description of the circuit using the signals in the sensitivity list. For example :
if(S1 = '1')then
S7 <= S5 xor S6; -- S7 does not have to be in the sensitivity list, it is not read
elsif(S2 = '1')then
S7 <= S3;
else
S7 <= S4;
end if;
end process;
```
### Implicit process
It is possible to describe the operation of a circuit outside an explicit process.
This is called an implicit process. Implicit processes are used when it is not necessary to use a process as such. Putting a permanent connection (assignment) between two signals in an explicit process is of no interest, it is done outside:
```.vhdl
process(...)
begin
...
end process;
A <= B and C; -- Implicit process here
process(...)
begin
...
end process;
```
## Conditionnal structures
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mkdocs.yml
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......@@ -54,7 +54,10 @@ nav:
- Types in VHDL: memo/types.md
- Operators: memo/operators.md
- A VHDL file: memo/vhdl-file.md
- Synthesizable VHDL examples: memo/synthesizable-vhdl.md
- Synthesizable VHDL examples:
- Introduction: memo/synthesizable-vhdl.md
- Process types: memo/process.md
- Conditional structures: conditional.md
- Non synthesizable VHDL examples: memo/non-synthesizable-vhdl.md
- Useful tools: memo/tools.md
- Sources: memo/sources.md
......
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