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synthhe update

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# Design of a digital synthesizer
## VHDL Cheat Sheet
[VHDL Cheat Sheet](../memo/index.md)
## gitlab repository
## Objective
A gitlab repository `tp-synthe-etudiant` is available in your gitlab space on [https://gitlab-df.imt-atlantique.fr](https://gitlab-df.imt-atlantique.fr), in the group corresponding to the course followed.
To manipulate it (`clone`, `add`, `commit`, `push`, `pull`), please refer to the page [Git and Gitlab ](../gitlab.md).
Your mission is to wire correctly all the building blocks of a digital synthesizer running on a digital circuit and then to **play the famous "Funkytown" melody (by Lipps Inc.) with the keyboard**.
The best player will be elected at the end of the lab.
If no repository creation is planned for your course, or if you want to do this lab freely. The reference repository is here: [https://gitlab.imt-atlantique.fr/tp-vhdl/tp-synthe-etudiant](https://gitlab.imt-atlantique.fr/tp-vhdl/tp-filtre-etudiant)
The digital processing core is a reconfigurable Field-Programmable Gate Array (FPGA), an Artix 7 by AMD, associated to peripherals on a board, the Digilent Nexys Video board, as illustrated on the figure below
![Nexys video board](../img/synthe/system.png#center#shadow)
## Objective
This lab offers a brief introduction to the design of digital integrated circuits with simple blocks to analyse and then then to interconnect.
This lab offers a brief introduction to the design of digital integrated circuits with simple blocks to analyse and then to interconnect.
Once wired, all the blocks process samples so that tones can be generated with orders coming from a USB keyboard.
Starting from blocks described in VHDL (a language dedicated to electronics), you will have to
1. analyse time diagrams of blocks to deduce their functions,
2. wire all the blocks together,
2. wire all the blocks together, by completing a VHDL file (wave_generator.vhd), based on your analysis of the time diagrams,
3. perform its synthesis,
3. test the resulting circuit on a reconfigurable Field-Programmable Gate Array (FPGA) circuit by playing some tones.
4. test the resulting circuit on an FPGA by playing some tones.
Block diagram of the circuit to design
!!! note
A VHDL code will be partially proposed to you, you will have to complete it, based on the preparatory work requested.
To synthesize tones, you can use visit this webpage:
https://www.szynalski.com/tone-generator/
ou can see that tones are associated to oscillation frequencies of different waveforms: sine, square, triangle or saw-tooth.
!!! info
For your information, know that FPGAs have held an essential place in high-end audiophile systems (such as those from PSaudio) for several years and are beginning to break into "consumer" products with high-resolution formats that FPGAs can fully exploit (as in the Chord Mojo for audiophile players).
## Synthesizing tones
To synthesize tones, you can use visit this webpage:
https://www.szynalski.com/tone-generator/
You can see that tones are associated to oscillation frequencies of different waveforms: sine, square, triangle or saw-tooth.
#### Work in the classroom
## Some useful documentation
You will use the Xilinx Vivado software to describe and synthesize your circuit based on the files available on the git repository.
During this lab sessions, ***you will complete the provided code of
The circuit to be configured is a Xilinx Artix 7 FPGA which is integrated on the Digilent Nexys Video board shown below and including, in addition to the FPGA, many peripherals.
![Nexys video board](../img/filtre/Nexysvideo.png#center#shadow)
The circuit to be configured is a Xilinx Artix 7 FPGA which is integrated on the Digilent Nexys Video board.
The documentation of the board is available here:
https://digilent.com/reference/programmable-logic/nexys-video/reference-manual
This documentation is *useful* to understand the use of the peripherals.
## gitlab repository
A gitlab repository `tp-synthe-etudiant` is available in your gitlab space on [https://gitlab-df.imt-atlantique.fr](https://gitlab-df.imt-atlantique.fr), in the group corresponding to the course followed.
To manipulate it (`clone`, `add`, `commit`, `push`, `pull`), please refer to the page [Git and Gitlab ](../gitlab.md).
If no repository creation is planned for your course, or if you want to do this lab freely. The reference repository is here: [https://gitlab.imt-atlantique.fr/tp-vhdl/tp-synthe-etudiant](https://gitlab.imt-atlantique.fr/tp-vhdl/tp-filtre-etudiant)
### Retrieving the gitlab project on [https://gitlab-df.imt-atlantique.fr](https://gitlab-df.imt-atlantique.fr)
......@@ -78,7 +78,9 @@ The `git clone` command allows you to retrieve the entire `git` repository with
You can easily see that this command has allowed you to download with the `ls -alsh` command in the `tp-filtre-etudiant-$USER` directory.
### Creating a Vivado project
## Digital circuit design
### Create a Vivado project
!!! warning
Never put **spaces**, **accents** or **special characters** in file or directory names! This is true in general, on Windows as well as on Linux. And it crashes Vivado in our case here.
......@@ -86,7 +88,7 @@ You can easily see that this command has allowed you to download with the `ls -a
Return to the user's home directory and launch Vivado
{%
include-markdown "launch-vivado.md"
include-markdown "vhdl/launch-vivado.md"
%}
A TCL script is provided to automate the project creation. To use it, you need to:
......@@ -103,3 +105,5 @@ A TCL script is provided to automate the project creation. To use it, you need t
shell commands `cd`, `ls`, `pwd` are usable in this console
This will create a complete project that will be deployed on FPGA.
### Run and analyse digital circuit simulations
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