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custom_dsp_16qam_tx.v

+
+// module custom_dsp_16qam_tx
+// #(
+//     parameter WIDTH = 24
+// )
+// (
+//     input clock,
+//     input reset,
+//     input clear,
+//     input enable,
+
+//     input set_stb,
+//     input [7:0] set_addr,
+//     input [31:0] set_data,
+
+//     output reg [WIDTH-1:0] frontend_i,
+//     output reg [WIDTH-1:0] frontend_q,
+
+//     input [WIDTH-1:0] duc_out_i,
+//     input [WIDTH-1:0] duc_out_q,
+
+//     output [31:0] duc_in_sample,
+//     input duc_in_strobe,
+//     output duc_in_enable,
+
+//     input [31:0] bb_sample,
+//     output bb_strobe
+// );
+
+//     // Registro para seleccionar el modo (0 = pass-through, 1 = QAM)
+//     reg dsp_mode;
+    
+//     always @(posedge clock) begin
+//         if (reset)
+//             dsp_mode <= 1'b0;
+//         else if (set_stb && (set_addr == 8'h2A))
+//             dsp_mode <= set_data[0];
+//     end
+
+//     // Modulación QAM
+//     reg [3:0] qam_data;
+//     wire [WIDTH-1:0] qam_i, qam_q;
+    
+//     always @(posedge clock) begin
+//         if (reset)
+//             qam_data <= 4'b0000;
+//         else if (duc_in_strobe)
+//             qam_data <= bb_sample[3:0];
+//     end
+
+//     cordic_z24 #(.bitwidth(WIDTH)) cordic_qam (
+//         .clock(clock),
+//         .reset(reset),
+//         .enable(dsp_mode),
+//         .xi({{(WIDTH-4){1'b0}}, qam_data[3:2], 2'b00}),
+//         .yi({{(WIDTH-4){1'b0}}, qam_data[1:0], 2'b00}),
+//         .zi(24'd0),
+//         .xo(qam_i),
+//         .yo(qam_q),
+//         .zo()
+//     );
+
+//     // Conexión al DUC
+//     assign duc_in_sample = dsp_mode ? {qam_q[23:8], qam_i[23:8]} : bb_sample;
+    
+//     // Salida al frontend (post-DUC)
+//     always @(posedge clock) begin
+//         frontend_i <= duc_out_i;
+//         frontend_q <= duc_out_q;
+//     end
+
+//     assign bb_strobe = duc_in_strobe;
+//     assign duc_in_enable = enable;
+
+// endmodule
+
+
+
+
+module custom_dsp_16qam_tx
+#(
+    parameter WIDTH = 24
+)
+(
+    input clock,
+    input reset,
+    input clear,
+    input enable,
+
+    input set_stb,
+    input [7:0] set_addr,
+    input [31:0] set_data,
+
+    output reg [WIDTH-1:0] frontend_i,
+    output reg [WIDTH-1:0] frontend_q,
+
+    input [WIDTH-1:0] duc_out_i,
+    input [WIDTH-1:0] duc_out_q,
+
+    output [31:0] duc_in_sample,
+    input duc_in_strobe,
+    output duc_in_enable,
+
+    input [31:0] bb_sample,
+    output bb_strobe
+);
+
+    // Registro para seleccionar el modo DSP 
+    wire [1:0] dsp_mode;
+    wire [1:0] dsp_mode_wire;
+    assign dsp_mode = dsp_mode_wire;
+
+    setting_reg #(
+        .my_addr(8'h2A),
+        .width(2)
+    ) dsp_control (
+        .clk(clock),
+        .rst(reset),
+        .strobe(set_stb),
+        .addr(set_addr),
+        .in(set_data),
+        .out(dsp_mode_wire),
+        .changed()
+    );
+
+    // Señal cuadrada para pass-through
+    reg [WIDTH-1:0] square_wave_i, square_wave_q;
+    reg square_state;
+    reg [15:0] square_counter;
+
+    always @(posedge clock) begin
+        if (reset) begin
+            square_state <= 1'b0;
+            square_wave_i <= {WIDTH{1'b0}};
+            square_wave_q <= {WIDTH{1'b0}};
+            square_counter <= 16'd0;
+        end else if (dsp_mode == 2'b00) begin
+            // Generar señal cuadrada con frecuencia ajustable
+            square_counter <= square_counter + 1;
+            
+            // Cambiar estado cada 1000 ciclos de reloj (ajustable)
+            if (square_counter == 16'd1000) begin
+                square_state <= ~square_state;
+                square_counter <= 16'd0;
+            end
+
+            // Asignar valores de amplitud máxima
+            square_wave_i <= square_state ? {WIDTH{1'b1}} : {WIDTH{1'b0}};
+            square_wave_q <= {WIDTH{1'b0}};
+        end
+    end
+
+    // 16QAM modulation
+    reg [3:0] qam_data;
+    wire [WIDTH-1:0] qam_i, qam_q;
+    
+    always @(posedge clock) begin
+        if (reset)
+            qam_data <= 4'b0000;
+        else if (bb_strobe)
+            qam_data <= bb_sample[3:0]; // Tomar los 4 bits menos significativos
+    end
+
+    // Módulo CORDIC para 16QAM
+    cordic_z24 #(.bitwidth(WIDTH)) cordic_qam (
+        .clock(clock),
+        .reset(reset),
+        .enable(dsp_mode == 2'b01),
+        .xi({{(WIDTH-4){1'b0}}, qam_data[3:2], 2'b00}),
+        .yi({{(WIDTH-4){1'b0}}, qam_data[1:0], 2'b00}),
+        .zi(24'd0), 
+        .xo(qam_i),
+        .yo(qam_q),
+        .zo()
+    );
+
+    // Frequency shift
+    reg [23:0] phase_acc;
+    wire [WIDTH-1:0] freq_shift_i, freq_shift_q;
+    
+    always @(posedge clock) begin
+        if (reset)
+            phase_acc <= 24'd0;
+        else if (dsp_mode == 2'b10)
+            phase_acc <= phase_acc + set_data[23:0]; 
+    end
+
+    // Módulo CORDIC para desplazamiento de frecuencia
+    cordic_z24 #(.bitwidth(WIDTH)) cordic_freq_shift (
+        .clock(clock),
+        .reset(reset),
+        .enable(dsp_mode == 2'b10),
+        .xi({bb_sample[15:0], {(WIDTH-16){1'b0}}}),  
+        .yi({bb_sample[31:16], {(WIDTH-16){1'b0}}}), 
+        .zi(phase_acc),
+        .xo(freq_shift_i),
+        .yo(freq_shift_q),
+        .zo()
+    );
+
+    // Multiplexación de salida
+    always @(posedge clock) begin
+        if (reset) begin
+            frontend_i <= {WIDTH{1'b0}};
+            frontend_q <= {WIDTH{1'b0}};
+        end else if (enable) begin
+            case (dsp_mode)
+                2'b00: begin // Pass-through mode (señal cuadrada)
+                    frontend_i <= square_wave_i;
+                    frontend_q <= square_wave_q;
+                end
+                2'b01: begin // 16QAM mode
+                    frontend_i <= qam_i;
+                    frontend_q <= qam_q;
+                end
+                2'b10: begin // Frequency shift mode
+                    frontend_i <= freq_shift_i;
+                    frontend_q <= freq_shift_q;
+                end
+                default: begin
+                    frontend_i <= duc_out_i;
+                    frontend_q <= duc_out_q;
+                end
+            endcase
+        end
+    end
+
+    // Modificación para enviar datos procesados al DUC
+    assign duc_in_sample = (dsp_mode == 2'b00) ? {square_wave_i[WIDTH-1:0], square_wave_q[WIDTH-1:0]} :
+                           (dsp_mode == 2'b01) ? {qam_i[WIDTH-1:0], qam_q[WIDTH-1:0]} :
+                           (dsp_mode == 2'b10) ? {freq_shift_i[WIDTH-1:0], freq_shift_q[WIDTH-1:0]} :
+                           bb_sample;
+
+    // Conexiones de entrada/salida
+    assign bb_strobe = duc_in_strobe;
+    assign duc_in_enable = enable;
+
+endmodule