Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2700185
date_generatedTue Feb 21 16:09:38 2023 os_platformLIN64
product_versionVivado v2019.2 (64-bit) project_id6737922d63e140f3b9b38e0796d63452
project_iteration1 random_ide0ee3123df9a5b6bb16658f36c076a97
registration_id210967703_174171490_210736846_660 route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagecsg324 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-6500 CPU @ 3.20GHz cpu_speed3205.327 MHz
os_nameUbuntu os_releaseUbuntu 20.04.5 LTS
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=2 addsrcwizard_specify_simulation_specific_hdl_files=3 basedialog_ok=23 basedialog_yes=1
basereporttab_rerun=2 constraintschooserpanel_add_files=1 expreporttreepanel_exp_report_tree_table=21 expruntreepanel_exp_run_tree_table=2
filesetpanel_file_set_panel_tree=241 filesetpanel_messages=1 flownavigatortreepanel_flow_navigator_tree=35 fpgachooser_family=1
fpgachooser_fpga_table=1 fpgachooser_package=1 gettingstartedview_open_project=3 graphicalview_zoom_fit=17
graphicalview_zoom_in=28 graphicalview_zoom_out=19 hinputhandler_toggle_line_comments=1 launchpanel_generate_scripts_only=1
mainmenumgr_checkpoint=9 mainmenumgr_export=5 mainmenumgr_file=22 mainmenumgr_ip=8
mainmenumgr_open_recent_project=2 mainmenumgr_project=12 mainmenumgr_text_editor=6 numjobschooser_number_of_jobs=1
pacommandnames_add_sources=9 pacommandnames_auto_update_hier=27 pacommandnames_close_project=7 pacommandnames_goto_netlist_design=1
pacommandnames_new_project=1 pacommandnames_open_project=1 pacommandnames_reports_window=2 pacommandnames_set_as_top=15
pacommandnames_simulation_live_break=5 pacommandnames_simulation_live_restart=45 pacommandnames_simulation_live_run=49 pacommandnames_simulation_live_run_all=4
pacommandnames_simulation_relaunch=1 pacommandnames_simulation_reset=1 pacommandnames_simulation_run=1 pacommandnames_simulation_run_behavioral=9
pacommandnames_upgrade_ip=1 paviews_code=8 paviews_par_report=4 paviews_project_summary=11
projectnamechooser_choose_project_location=1 projectnamechooser_project_name=1 rdiviews_waveform_viewer=18 reportipstatusinfodialog_ignore=1
reportipstatusinfodialog_report_ip_status=1 saveprojectutils_save=4 simpleoutputproductdialog_generate_output_products_immediately=1 simulationliverunforcomp_specify_time_and_units=22
simulationobjectspanel_simulation_objects_tree_table=91 simulationscopespanel_simulate_scope_table=51 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=9 srcmenu_ip_hierarchy=29
syntheticagettingstartedview_recent_projects=4 tclconsoleview_clear_all_output_in_tcl_console=1 tclconsoleview_tcl_console_code_editor=1 waveformfindbar_close=1
waveformfindbar_find_by=1 waveformnametree_waveform_name_tree=72 waveformview_goto_last_time=1 waveformview_goto_time_0=17
java_command_handlers
addsources=9 closeproject=7 newproject=1 openhardwaremanager=1
openproject=4 reportipstatus=1 runbitgen=1 runsynthesis=7
savefileproxyhandler=1 settopnode=15 showview=4 simulationbreak=5
simulationrelaunch=2 simulationrestart=45 simulationrun=9 simulationrunall=4
simulationrunfortime=49 toggleviewnavigator=4 upgradeip=1 viewtaskprojectmanager=6
viewtasksimulation=1 waveformsaveconfiguration=1
other_data
guimode=10
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=2 export_simulation_ies=2
export_simulation_modelsim=2 export_simulation_questa=2 export_simulation_riviera=2 export_simulation_vcs=2
export_simulation_xsim=2 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=13 simulator_language=Mixed srcsetcount=12 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=2 carry4=87 fdce=100 fdpe=17
fdre=83 gnd=7 ibuf=3 lut1=60
lut2=258 lut3=71 lut4=46 lut5=41
lut6=60 mmcme2_adv=1 obuf=14 ramb36e1=5
vcc=8
pre_unisim_transformation
bufg=2 carry4=87 fdce=100 fdpe=17
fdre=83 gnd=7 ibuf=3 lut1=60
lut2=258 lut3=71 lut4=46 lut5=41
lut6=60 mmcme2_adv=1 obuf=14 ramb36e1=5
vcc=8

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=10 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=200 srls_augmented=0
srls_newly_gated=0 srls_total=0

ip_statistics
clk_wiz_v6_0_4_0_0/1
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=NA component_name=clk_wiz_vga_25MHz
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=false

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 check-3=1 reqp-1839=20

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
synth-16=1 xdcc-1=1 xdcc-7=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.002719 clocks=0.000855
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Medium confidence_level_overall=Medium customer=TBD customer_class=TBD
devstatic=0.097679 die=xc7a100tcsg324-1 dsp_output_toggle=12.500000 dynamic=0.121119
effective_thetaja=4.6 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.000251 input_toggle=12.500000
junction_temp=26.0 (C) logic=0.000669 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.116009 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.218798 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=csg324 pct_clock_constrained=1.190000 pct_inputs_defined=33
platform=lin64 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.000615
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=5.7 (C/W) thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=4.6 user_junc_temp=26.0 (C) user_thetajb=5.7 (C/W) user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.064311 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.018166 vccaux_total_current=0.082477 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000224 vccbram_static_current=0.000369 vccbram_total_current=0.000593 vccbram_voltage=1.000000
vccint_dynamic_current=0.004961 vccint_static_current=0.015412 vccint_total_current=0.020373 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.000053 vcco33_static_current=0.004000 vcco33_total_current=0.004053 vcco33_voltage=3.300000
version=2019.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=96 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=24 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=12 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=16.67
plle2_adv_available=6 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=240 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_used=5 block_ram_tile_util_percentage=3.70
ramb18_available=270 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=135 ramb36_fifo_fixed=0 ramb36_fifo_used=5 ramb36_fifo_util_percentage=3.70
ramb36e1_only_used=5
primitives
bufg_functional_category=Clock bufg_used=2 carry4_functional_category=CarryLogic carry4_used=87
fdce_functional_category=Flop & Latch fdce_used=100 fdpe_functional_category=Flop & Latch fdpe_used=17
fdre_functional_category=Flop & Latch fdre_used=83 ibuf_functional_category=IO ibuf_used=3
lut1_functional_category=LUT lut1_used=59 lut2_functional_category=LUT lut2_used=258
lut3_functional_category=LUT lut3_used=71 lut4_functional_category=LUT lut4_used=46
lut5_functional_category=LUT lut5_used=41 lut6_functional_category=LUT lut6_used=60
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 obuf_functional_category=IO obuf_used=14
ramb36e1_functional_category=Block Memory ramb36e1_used=5
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=63400 lut_as_logic_fixed=0 lut_as_logic_used=367 lut_as_logic_util_percentage=0.58
lut_as_memory_available=19000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=200 register_as_flip_flop_util_percentage=0.16
register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=63400 slice_luts_fixed=0 slice_luts_used=367 slice_luts_util_percentage=0.58
slice_registers_available=126800 slice_registers_fixed=0 slice_registers_used=200 slice_registers_util_percentage=0.16
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=367 lut_as_logic_util_percentage=0.58 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=56 lut_in_front_of_the_register_is_used_fixed=56 lut_in_front_of_the_register_is_used_used=38
register_driven_from_outside_the_slice_fixed=38 register_driven_from_outside_the_slice_used=94 register_driven_from_within_the_slice_fixed=94 register_driven_from_within_the_slice_used=106
slice_available=15850 slice_fixed=0 slice_registers_available=126800 slice_registers_fixed=0
slice_registers_used=200 slice_registers_util_percentage=0.16 slice_used=152 slice_util_percentage=0.96
slicel_fixed=0 slicel_used=108 slicem_fixed=0 slicem_used=44
unique_control_sets_available=15850 unique_control_sets_fixed=15850 unique_control_sets_used=14 unique_control_sets_util_percentage=0.09
using_o5_and_o6_fixed=0.09 using_o5_and_o6_used=168 using_o5_output_only_fixed=168 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=199
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a100tcsg324-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=sobelSys -verilog_define=default::[not_specified]
usage
elapsed=00:00:55s hls_ip=0 memory_gain=661.367MB memory_peak=2184.223MB

xsim
command_line_options
-sim_mode=behavioral -sim_type=default::