From f9a2383b318c551f79717c7fe8a530862fe9265c Mon Sep 17 00:00:00 2001
From: Jean-Noel Bazin <jn.bazin@imt-atlantique.fr>
Date: Thu, 27 Feb 2025 13:57:34 +0100
Subject: [PATCH] Update sources, reports and figures
---
.../sobel-address-generator-student.drawio | 40 ++
docs/img/sobel-address-generator-student.png | Bin 0 -> 357082 bytes
docs/report.md | 55 +-
src/DualPortRamGeneric.vhd | 109 ++--
src/SinglePortROMFileInitGeneric.vhd | 114 ++--
src/sobelProc.vhd | 288 +++++----
src/sobelSys.vhd | 383 ++++++------
src/tb_adrgenUnit.vhd | 134 ++---
src/tb_automate.vhd | 118 ++--
src/tb_gradientUnit.vhd | 75 ++-
src/tb_operativeUnit.vhd | 103 ++--
src/tb_regUnit.vhd | 108 ++--
src/tb_sobelProc.vhd | 93 ++-
src/tb_sobelSys.vhd | 78 ++-
src/vga_nexys4_2regions.vhd | 560 +++++++++---------
15 files changed, 1133 insertions(+), 1125 deletions(-)
create mode 100644 docs/img/sobel-address-generator-student.drawio
create mode 100644 docs/img/sobel-address-generator-student.png
diff --git a/docs/img/sobel-address-generator-student.drawio b/docs/img/sobel-address-generator-student.drawio
new file mode 100644
index 0000000..bb5758c
--- /dev/null
+++ b/docs/img/sobel-address-generator-student.drawio
@@ -0,0 +1,40 @@
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diff --git a/docs/img/sobel-address-generator-student.png b/docs/img/sobel-address-generator-student.png
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diff --git a/docs/report.md b/docs/report.md
index 6f9b068..de1fcc0 100644
--- a/docs/report.md
+++ b/docs/report.md
@@ -3,70 +3,79 @@
Name:
Name:
-## Question 1: What is the nature of the VHDL process that describes the register bank? Its sensitivity list? Did the functional simulation validate the module? Justify
+## Operative Unit
+### Question 1: What is the nature of the VHDL process that describes the register bank? Its sensitivity list? Did the functional simulation validate the module? Justify
-## Question 2: Give the results obtained
+### Question 2: Give the results obtained
-## Question 3: What type and quantification did you use for the internal signals? Justify.
+### Question 3: What type and quantification did you use for the internal signals? Justify.
-## Question 4: How many processes are used and what are their natures? Sensitivity list? Did the functional simulation validate the module? Justify
+### Question 4: How many processes are used and what are their natures? Sensitivity list? Did the functional simulation validate the module? Justify
-## Question 5: Give the results obtained
+### Question 5: Give the results obtained
-## Question 6: Did the functional simulation validate the module? Justify
+### Question 6: Did the functional simulation validate the module? Justify
-## Question 7: Give and comment on the results obtained
+### Question 7: Give and comment on the results obtained
-## Question 8: Give the architecture you propose for the address generator
+## Address Generator
+### Question 8: Give the architecture you propose for the address generator
-## Question 9: Did the functional simulation validate the module? Justify
+This diagram is to be completed in order to then complete the VHDL file `addGenUnit.vhd`. To do this, you can use the file `sobel-address-generator-student.drawio` available in the git repository, it is the file `docs/img/sobel-address-generator-student.drawio` with the tool [https://app.diagrams.net/](https://app.diagrams.net/). Then update the file `sobel-address-generator-student.png` by exporting the diagram `sobel-address-generator-student.drawio` previously updated.
+
-## Question 10: Give the results obtained
+### Question 9: Did the functional simulation validate the module? Justify
-## Question 11: Complete the state machine diagram
+### Question 10: Give the results obtained
-!!! info
- This diagram is to be completed in order to then complete the VHDL file `automate.vhd`. To do this, you can use the file `automate.drawio` available in the git repository, it is the file `docs/img/automate.drawio` with the tool [https://app.diagrams.net/](https://app.diagrams.net/). Then update the file `automate.png` by exporting the diagram `automate.drawio` previously updated.
+## Finite State Machine (FSM)
+
+### Question 11: Complete the state machine diagram
+
+
+This diagram is to be completed in order to then complete the VHDL file `automate.vhd`. To do this, you can use the file `sobel-FSM.drawio` available in the git repository, it is the file `docs/img/sobel-FSM.drawio` with the tool [https://app.diagrams.net/](https://app.diagrams.net/). Then update the file `sobel-FSM.png` by exporting the diagram `sobel-FSM.drawio` previously updated.
-## Question 12: How many processes are used to describe the FSM, and what are their natures? Their sensitivity lists? Did the functional simulation validate the module? Justify
+### Question 12: How many processes are used to describe the FSM, and what are their natures? Their sensitivity lists? Did the functional simulation validate the module? Justify
-## Question 13: Give the results obtained
+### Question 13: Give the results obtained
+## Integration of the processor and prototyping
-## Question 14: Did the functional simulation validate the module? Justify
+### Question 14: Did the functional simulation validate the module? Justify
-## Question 15: Give and comment on the results obtained. What is the percentage of resources used by the Sobel processor compared to those available on the target Artix 7 FPGA `XC7A100T-CSG324-1`. Comment
+### Question 15: Give and comment on the results obtained. What is the percentage of resources used by the Sobel processor compared to those available on the target Artix 7 FPGA `XC7A100T-CSG324-1`. Comment
-## Question 16: Give and comment on the results obtained.
+### Question 16: Give and comment on the results obtained.
-## Question 17: Is the prototyping and demonstration on the board conclusive?
+### Question 17: Is the prototyping and demonstration on the board conclusive?
+## Performance analysis
-## Question 18: Identify the maximum clock frequency achievable on this FPGA
+### Question 18: Identify the maximum clock frequency achievable on this FPGA
-## Question 19: How many clock cycles are needed to process a pixel?
+### Question 19: How many clock cycles are needed to process a pixel?
-## Question 20: How many clock cycles are needed to process a 396x396 definition image
+### Question 20: How many clock cycles are needed to process a 396x396 definition image
-## Question 21: How many 396x396 definition images can this processor process per second?
+### Question 21: How many 396x396 definition images can this processor process per second?
diff --git a/src/DualPortRamGeneric.vhd b/src/DualPortRamGeneric.vhd
index ba0da50..b66e36e 100644
--- a/src/DualPortRamGeneric.vhd
+++ b/src/DualPortRamGeneric.vhd
@@ -9,56 +9,56 @@ use ieee.numeric_std.all;
entity DualPortRamGeneric is
generic(
- G_MemoryWidth : integer;
- G_MemoryDepth : integer;
- G_AddressWidth : integer
- );
- port (
- I_clk : in std_logic;
- I_ena : in std_logic;
- I_enb : in std_logic;
- I_wea : in std_logic;
- I_addra : in std_logic_vector(G_AddressWidth-1 downto 0);
- I_addrb : in std_logic_vector(G_AddressWidth-1 downto 0);
- I_dina : in std_logic_vector(G_MemoryWidth-1 downto 0);
- O_douta : out std_logic_vector(G_MemoryWidth-1 downto 0);
- O_doutb : out std_logic_vector(G_MemoryWidth-1 downto 0)
- );
+ G_MemoryWidth : integer;
+ G_MemoryDepth : integer;
+ G_AddressWidth : integer
+ );
+ port (
+ I_clk : in std_logic;
+ I_ena : in std_logic;
+ I_enb : in std_logic;
+ I_wea : in std_logic;
+ I_addra : in std_logic_vector(G_AddressWidth-1 downto 0);
+ I_addrb : in std_logic_vector(G_AddressWidth-1 downto 0);
+ I_dina : in std_logic_vector(G_MemoryWidth-1 downto 0);
+ O_douta : out std_logic_vector(G_MemoryWidth-1 downto 0);
+ O_doutb : out std_logic_vector(G_MemoryWidth-1 downto 0)
+ );
end DualPortRamGeneric;
architecture rtl of DualPortRamGeneric is
- type ram_type is array (0 to G_MemoryDepth-1) of std_logic_vector(G_MemoryWidth-1 downto 0);
- signal RAM : ram_type := (others => (others => '1')); -- attention initialisation � '1'
- signal read_addra : std_logic_vector(G_AddressWidth-1 downto 0);
- signal read_addrb : std_logic_vector(G_AddressWidth-1 downto 0);
+ type ram_type is array (0 to G_MemoryDepth-1) of std_logic_vector(G_MemoryWidth-1 downto 0);
+ signal RAM : ram_type := (others => (others => '1')); -- attention initialisation � '1'
+ signal read_addra : std_logic_vector(G_AddressWidth-1 downto 0);
+ signal read_addrb : std_logic_vector(G_AddressWidth-1 downto 0);
begin
-- pragma synthesis_off
- assert (not( G_MemoryDepth > 2**G_AddressWidth))
- report "bad value for G_MemoryDepth or G_AddressWidth"
- severity error;
+ assert (not(G_MemoryDepth > 2**G_AddressWidth))
+ report "bad value for G_MemoryDepth or G_AddressWidth"
+ severity error;
-- pragma synthesis_on
- process (I_clk)
- begin
- if (I_clk'event and I_clk = '1') then
- if (I_ena = '1') then
- if (I_wea = '1') then
- RAM(to_integer(unsigned(I_addra))) <= I_dina;
- end if;
- read_addra <= I_addra;
- end if;
- if (I_enb = '1') then
- read_addrb <= I_addrb;
- end if;
- end if;
- end process;
-
- O_douta <= RAM(to_integer(unsigned(read_addra)));
- O_doutb <= RAM(to_integer(unsigned(read_addrb)));
+ process (I_clk)
+ begin
+ if (I_clk'event and I_clk = '1') then
+ if (I_ena = '1') then
+ if (I_wea = '1') then
+ RAM(to_integer(unsigned(I_addra))) <= I_dina;
+ end if;
+ read_addra <= I_addra;
+ end if;
+ if (I_enb = '1') then
+ read_addrb <= I_addrb;
+ end if;
+ end if;
+ end process;
+
+ O_douta <= RAM(to_integer(unsigned(read_addra)));
+ O_doutb <= RAM(to_integer(unsigned(read_addrb)));
end rtl;
@@ -73,15 +73,15 @@ end rtl;
-- G_AddressWidth : Integer
-- );
--port (
--- I_clk : in std_logic;
--- I_ena : in std_logic;
--- I_enb : in std_logic;
--- I_wea : in std_logic;
--- I_addra : in std_logic_vector(G_AddressWidth-1 downto 0);
--- I_addrb : in std_logic_vector(G_AddressWidth-1 downto 0);
--- I_dina : in std_logic_vector(G_MemoryWidth-1 downto 0);
--- O_douta : out std_logic_vector(G_MemoryWidth-1 downto 0);
--- O_doutb : out std_logic_vector(G_MemoryWidth-1 downto 0)
+-- I_clk : in std_logic;
+-- I_ena : in std_logic;
+-- I_enb : in std_logic;
+-- I_wea : in std_logic;
+-- I_addra : in std_logic_vector(G_AddressWidth-1 downto 0);
+-- I_addrb : in std_logic_vector(G_AddressWidth-1 downto 0);
+-- I_dina : in std_logic_vector(G_MemoryWidth-1 downto 0);
+-- O_douta : out std_logic_vector(G_MemoryWidth-1 downto 0);
+-- O_doutb : out std_logic_vector(G_MemoryWidth-1 downto 0)
-- );
--end component;
@@ -94,17 +94,12 @@ end rtl;
-- )
-- port map (
-- I_clk => clk,
--- I_ena => ena,
--- I_enb => enb,
--- I_wea => wea,
+-- I_ena => ena,
+-- I_enb => enb,
+-- I_wea => wea,
-- I_addra => addra,
-- I_addrb => addrb,
--- I_dina => dina,
+-- I_dina => dina,
-- O_douta => douta,
-- O_doutb => doutb
-- );
-
-
-
-
-
diff --git a/src/SinglePortROMFileInitGeneric.vhd b/src/SinglePortROMFileInitGeneric.vhd
index 6c6ff09..2393b18 100644
--- a/src/SinglePortROMFileInitGeneric.vhd
+++ b/src/SinglePortROMFileInitGeneric.vhd
@@ -1,67 +1,67 @@
-------------------------------------------------------------------------------
--- Generic Single Port ROM initialized with a specified file
+-- Generic Single Port ROM initialized with a specified file
--
-Library ieee;
-Use ieee.std_logic_1164.All;
-Use ieee.numeric_std.All;
-Use std.textio.All;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
-Entity SinglePortROMFileInitGeneric Is
- Generic (
- G_MemoryWidth : Integer;
- G_MemoryDepth : Integer;
- G_AddressWidth : Integer;
- G_InitFileName : String
- );
- Port (
- I_clk : In std_logic;
- I_en : In std_logic;
- I_addr : In std_logic_vector(G_AddressWidth - 1 Downto 0);
- O_dout : Out std_logic_vector(G_MemoryWidth - 1 Downto 0)
- );
-End SinglePortROMFileInitGeneric;
+entity SinglePortROMFileInitGeneric is
+ generic (
+ G_MemoryWidth : integer;
+ G_MemoryDepth : integer;
+ G_AddressWidth : integer;
+ G_InitFileName : string
+ );
+ port (
+ I_clk : in std_logic;
+ I_en : in std_logic;
+ I_addr : in std_logic_vector(G_AddressWidth - 1 downto 0);
+ O_dout : out std_logic_vector(G_MemoryWidth - 1 downto 0)
+ );
+end SinglePortROMFileInitGeneric;
-Architecture rtl Of SinglePortROMFileInitGeneric Is
+architecture rtl of SinglePortROMFileInitGeneric is
-type ramtype is array (G_MemoryDepth-1 downto 0) of std_logic_vector (G_MemoryWidth-1 downto 0); -- 2D Array Declaration for RAM signal
+ type ramtype is array (G_MemoryDepth-1 downto 0) of std_logic_vector (G_MemoryWidth-1 downto 0); -- 2D Array Declaration for RAM signal
-impure function initramfromfile (ramfilename : in string) return ramtype is
-file ramfile : text is in ramfilename;
-variable ramfileline : line;
-variable ram_name : ramtype;
-variable bitvec : bit_vector(G_MemoryWidth-1 downto 0);
-begin
- for i in ramtype'range loop
- readline (ramfile, ramfileline);
- exit when endfile (ramfile);
- read (ramfileline, bitvec);
- ram_name(i) := to_stdlogicvector(bitvec);
- end loop;
- return ram_name;
-end function;
+ impure function initramfromfile (ramfilename : in string) return ramtype is
+ file ramfile : text is in ramfilename;
+ variable ramfileline : line;
+ variable ram_name : ramtype;
+ variable bitvec : bit_vector(G_MemoryWidth-1 downto 0);
+ begin
+ for i in ramtype'range loop
+ readline (ramfile, ramfileline);
+ exit when endfile (ramfile);
+ read (ramfileline, bitvec);
+ ram_name(i) := to_stdlogicvector(bitvec);
+ end loop;
+ return ram_name;
+ end function;
-Signal RAM : RamType := InitRamFromFile(G_InitFileName);
+ signal RAM : RamType := InitRamFromFile(G_InitFileName);
-Begin
+begin
-- pragma synthesis_off
- assert (not( G_MemoryDepth > 2**G_AddressWidth))
- report "bad value for G_MemoryDepth or G_AddressWidth"
- severity error;
+ assert (not(G_MemoryDepth > 2**G_AddressWidth))
+ report "bad value for G_MemoryDepth or G_AddressWidth"
+ severity error;
-- pragma synthesis_on
- Process (I_clk)
- Begin
- If I_clk'EVENT and I_clk = '1' Then
- If I_en = '1' Then
- O_dout <= RAM(to_integer(unsigned(I_addr))); ---- uncomment to implement on BLOCK RAM
- End If;
- End If;
- End Process;
-
- -- O_dout <= RAM(to_integer(unsigned(I_addr))); ---- uncomment to implement on LUT
-End rtl;
+ process (I_clk)
+ begin
+ if I_clk'event and I_clk = '1' then
+ if I_en = '1' then
+ O_dout <= RAM(to_integer(unsigned(I_addr))); ---- uncomment to implement on BLOCK RAM
+ end if;
+ end if;
+ end process;
+
+-- O_dout <= RAM(to_integer(unsigned(I_addr))); ---- uncomment to implement on LUT
+end rtl;
-- The following is an instantiation template
@@ -73,13 +73,13 @@ End rtl;
-- G_MemoryWidth : Integer;
-- G_MemoryDepth : Integer;
-- G_AddressWidth : Integer;
--- G_InitFileName : String
+-- G_InitFileName : String
-- );
--port (
--- I_clk : In std_logic;
--- I_en : In std_logic;
--- I_addr : In std_logic_vector(G_AddressWidth - 1 Downto 0);
--- O_dout : Out std_logic_vector(G_MemoryWidth - 1 Downto 0)
+-- I_clk : In std_logic;
+-- I_en : In std_logic;
+-- I_addr : In std_logic_vector(G_AddressWidth - 1 Downto 0);
+-- O_dout : Out std_logic_vector(G_MemoryWidth - 1 Downto 0)
-- );
--end component;
@@ -89,7 +89,7 @@ End rtl;
-- G_MemoryWidth => 8,
-- G_MemoryDepth => 10000,
-- G_AddressWidth => 14,
--- G_InitFileName => "SobelMemIn.txt"
+-- G_InitFileName => "SobelMemIn.txt"
-- )
-- port map (
-- I_clk => clk,
diff --git a/src/sobelProc.vhd b/src/sobelProc.vhd
index 47d8591..e801a32 100644
--- a/src/sobelProc.vhd
+++ b/src/sobelProc.vhd
@@ -1,156 +1,154 @@
library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-
-entity sobelProc is
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- I_go : in STD_LOGIC;
- -- interface avec la mémoire IN (lecture)
- O_enM_R : out STD_LOGIC;
- O_ADR_R : out STD_LOGIC_VECTOR (13 downto 0);
- I_pixel : in STD_LOGIC_VECTOR (7 downto 0); -- Pixel from memory IN
- -- interface avec la mémoire OUT (écriture)
- O_enM_W : out STD_LOGIC;
- O_ADR_W : out STD_LOGIC_VECTOR (13 downto 0);
- O_pixEdge : out STD_LOGIC; -- Edge to memory OUT
- -- signal de commande vers le contrôleur VGA
- O_StartDisplay : out STD_LOGIC
- );
-end sobelProc;
-
-
-architecture Behavioral of sobelProc is
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+entity sobelProc is
+ port (I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_go : in std_logic;
+ -- interface avec la mémoire IN (lecture)
+ O_enM_R : out std_logic;
+ O_ADR_R : out std_logic_vector (13 downto 0);
+ I_pixel : in std_logic_vector (7 downto 0); -- Pixel from memory IN
+ -- interface avec la mémoire OUT (écriture)
+ O_enM_W : out std_logic;
+ O_ADR_W : out std_logic_vector (13 downto 0);
+ O_pixEdge : out std_logic; -- Edge to memory OUT
+ -- signal de commande vers le contrôleur VGA
+ O_StartDisplay : out std_logic
+ );
+end sobelProc;
+
+
+architecture Behavioral of sobelProc is
-- déclaration des sous-composants
- -- unité opérative
- component operativeUnit is
- port (clk,reset :in STD_LOGIC;
- I_pixel : in STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
- I_ldPix11 : in STD_LOGIC;
- I_ldPix21 : in STD_LOGIC;
- I_ldPix31 : in STD_LOGIC;
- I_shReg : in STD_LOGIC;
- I_ldPixEdge : in STD_LOGIC;
- O_pixEdge : out STD_LOGIC
- );
- end component operativeUnit;
-
- -- générateur d'adresses
- component adrgenUnit is
- port ( clk,reset : in STD_LOGIC;
- I_clr_PtrLine : in STD_LOGIC;
- I_inc_PtrLine : in STD_LOGIC;
- I_clr_PtrCol : in STD_LOGIC;
- I_inc_PtrCol : in STD_LOGIC;
- I_selPix : in STD_LOGIC_VECTOR (1 downto 0);
- O_EndImage : out STD_LOGIC;
- O_NewLine : out STD_LOGIC;
- O_ADR_R : out STD_LOGIC_VECTOR (13 downto 0);
- O_ADR_W : out STD_LOGIC_VECTOR (13 downto 0)
- );
- end component adrgenUnit;
-
- -- automate
- component automate is
- Port (clk,reset : in STD_LOGIC;
- I_go : in STD_LOGIC;
- I_EndImage : in STD_LOGIC;
- I_NewLine : in STD_LOGIC;
- -- signaux de commandes vers l'unité opérative
- O_ldPix11 : out STD_LOGIC;
- O_ldPix21 : out STD_LOGIC;
- O_ldPix31 : out STD_LOGIC;
- O_shReg : out STD_LOGIC;
- O_ldPixEdge : out STD_LOGIC;
- -- signaux de commandes vers le générateur d'adresses
- O_clr_PtrLine : out STD_LOGIC;
- O_inc_PtrLine : out STD_LOGIC;
- O_clr_PtrCol : out STD_LOGIC;
- O_inc_PtrCol : out STD_LOGIC;
- O_selPix : out STD_LOGIC_VECTOR (1 downto 0);
- -- signaux de commandes vers les mémoires
- O_enM_R : out STD_LOGIC;
- O_enM_W : out STD_LOGIC;
- -- signal de commande vers le contrôleur VGA
- O_StartDisplay : out STD_LOGIC
- );
- end component automate;
-
+ -- unité opérative
+ component operativeUnit is
+ port (I_clk : in std_logic;
+ I_pixel : in std_logic_vector (7 downto 0); -- Pixel from the memory
+ I_ldPix11 : in std_logic;
+ I_ldPix21 : in std_logic;
+ I_ldPix31 : in std_logic;
+ I_shReg : in std_logic;
+ I_ldPixEdge : in std_logic;
+ O_pixEdge : out std_logic
+ );
+ end component operativeUnit;
+
+ -- générateur d'adresses
+ component adrgenUnit is
+ port (I_clk : in std_logic;
+ I_clr_PtrLine : in std_logic;
+ I_inc_PtrLine : in std_logic;
+ I_clr_PtrCol : in std_logic;
+ I_inc_PtrCol : in std_logic;
+ I_selPix : in std_logic_vector (1 downto 0);
+ O_EndImage : out std_logic;
+ O_NewLine : out std_logic;
+ O_ADR_R : out std_logic_vector (13 downto 0);
+ O_ADR_W : out std_logic_vector (13 downto 0)
+ );
+ end component adrgenUnit;
+
+ -- automate
+ component automate is
+ port (I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_go : in std_logic;
+ I_EndImage : in std_logic;
+ I_NewLine : in std_logic;
+ -- signaux de commandes vers l'unité opérative
+ O_ldPix11 : out std_logic;
+ O_ldPix21 : out std_logic;
+ O_ldPix31 : out std_logic;
+ O_shReg : out std_logic;
+ O_ldPixEdge : out std_logic;
+ -- signaux de commandes vers le générateur d'adresses
+ O_clr_PtrLine : out std_logic;
+ O_inc_PtrLine : out std_logic;
+ O_clr_PtrCol : out std_logic;
+ O_inc_PtrCol : out std_logic;
+ O_selPix : out std_logic_vector (1 downto 0);
+ -- signaux de commandes vers les mémoires
+ O_enM_R : out std_logic;
+ O_enM_W : out std_logic;
+ -- signal de commande vers le contrôleur VGA
+ O_StartDisplay : out std_logic
+ );
+ end component automate;
+
-- déclaration des signaux internes
-signal S_EndImage : STD_LOGIC;
-signal S_NewLine : STD_LOGIC;
-signal S_ldPix11 : STD_LOGIC;
-signal S_ldPix21 : STD_LOGIC;
-signal S_ldPix31 : STD_LOGIC;
-signal S_shReg : STD_LOGIC;
-signal S_ldPixEdge : STD_LOGIC;
-signal S_clr_PtrLine : STD_LOGIC;
-signal S_inc_PtrLine : STD_LOGIC;
-signal S_clr_PtrCol : STD_LOGIC;
-signal S_inc_PtrCol : STD_LOGIC;
-signal S_selPix : STD_LOGIC_VECTOR (1 downto 0);
-
+ signal S_EndImage : std_logic;
+ signal S_NewLine : std_logic;
+ signal S_ldPix11 : std_logic;
+ signal S_ldPix21 : std_logic;
+ signal S_ldPix31 : std_logic;
+ signal S_shReg : std_logic;
+ signal S_ldPixEdge : std_logic;
+ signal S_clr_PtrLine : std_logic;
+ signal S_inc_PtrLine : std_logic;
+ signal S_clr_PtrCol : std_logic;
+ signal S_inc_PtrCol : std_logic;
+ signal S_selPix : std_logic_vector (1 downto 0);
+
begin
-- instanciation des sous-composants et établissement des interconnexions
-
- -- instanciation de l'unité opérative
- operativeUnit_1 : entity work.operativeUnit
- port map (
- clk => clk,
- reset => reset,
- I_pixel => I_pixel,
- I_ldPix11 => S_ldPix11,
- I_ldPix21 => S_ldPix21,
- I_ldPix31 => S_ldPix31,
- I_shReg => S_shReg,
- I_ldPixEdge => S_ldPixEdge,
- O_pixEdge => O_pixEdge
- );
-
- -- instanciation du générateur d'adresses
- adrgenUnit_1 : entity work.adrgenUnit
- port map (
- clk => clk,
- reset => reset,
- I_clr_PtrLine => S_clr_PtrLine,
- I_inc_PtrLine => S_inc_PtrLine,
- I_clr_PtrCol => S_clr_PtrCol,
- I_inc_PtrCol => S_inc_PtrCol,
- I_selPix => S_selPix,
- O_EndImage => S_EndImage,
- O_NewLine => S_NewLine,
- O_ADR_R => O_ADR_R,
- O_ADR_W => O_ADR_W
- );
-
- -- instanciation de l'automate
- automate_1 : entity work.automate
- port map (
- clk => clk,
- reset => reset,
- I_go => I_go,
- I_EndImage => S_EndImage,
- I_NewLine => S_NewLine,
- O_ldPix11 => S_ldPix11,
- O_ldPix21 => S_ldPix21,
- O_ldPix31 => S_ldPix31,
- O_shReg => S_shReg,
- O_ldPixEdge => S_ldPixEdge,
- O_clr_PtrLine => S_clr_PtrLine,
- O_inc_PtrLine => S_inc_PtrLine,
- O_clr_PtrCol => S_clr_PtrCol,
- O_inc_PtrCol => S_inc_PtrCol,
- O_selPix => S_selPix,
- O_enM_R => O_enM_R,
- O_enM_W => O_enM_W,
- O_StartDisplay => O_StartDisplay
- );
-
-end Behavioral;
+ -- instanciation de l'unité opérative
+ operativeUnit_1 : entity work.operativeUnit
+ port map (
+ I_clk => I_clk,
+ I_pixel => I_pixel,
+ I_ldPix11 => S_ldPix11,
+ I_ldPix21 => S_ldPix21,
+ I_ldPix31 => S_ldPix31,
+ I_shReg => S_shReg,
+ I_ldPixEdge => S_ldPixEdge,
+ O_pixEdge => O_pixEdge
+ );
+
+ -- instanciation du générateur d'adresses
+ adrgenUnit_1 : entity work.adrgenUnit
+ port map (
+ I_clk => I_clk,
+ I_clr_PtrLine => S_clr_PtrLine,
+ I_inc_PtrLine => S_inc_PtrLine,
+ I_clr_PtrCol => S_clr_PtrCol,
+ I_inc_PtrCol => S_inc_PtrCol,
+ I_selPix => S_selPix,
+ O_EndImage => S_EndImage,
+ O_NewLine => S_NewLine,
+ O_ADR_R => O_ADR_R,
+ O_ADR_W => O_ADR_W
+ );
+
+ -- instanciation de l'automate
+ automate_1 : entity work.automate
+ port map (
+ I_clk => I_clk,
+ I_rst => I_rst,
+ I_go => I_go,
+ I_EndImage => S_EndImage,
+ I_NewLine => S_NewLine,
+ O_ldPix11 => S_ldPix11,
+ O_ldPix21 => S_ldPix21,
+ O_ldPix31 => S_ldPix31,
+ O_shReg => S_shReg,
+ O_ldPixEdge => S_ldPixEdge,
+ O_clr_PtrLine => S_clr_PtrLine,
+ O_inc_PtrLine => S_inc_PtrLine,
+ O_clr_PtrCol => S_clr_PtrCol,
+ O_inc_PtrCol => S_inc_PtrCol,
+ O_selPix => S_selPix,
+ O_enM_R => O_enM_R,
+ O_enM_W => O_enM_W,
+ O_StartDisplay => O_StartDisplay
+ );
+
+end Behavioral;
diff --git a/src/sobelSys.vhd b/src/sobelSys.vhd
index b71dc88..6cfad74 100644
--- a/src/sobelSys.vhd
+++ b/src/sobelSys.vhd
@@ -1,216 +1,213 @@
library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
-entity sobelSys is
- Port ( clk_i : in STD_LOGIC;
- reset_i : in STD_LOGIC;
- go_i : in STD_LOGIC;
- -- VGA Output Signals
- vga_hs_o : out STD_LOGIC; -- HSYNC OUT
- vga_vs_o : out STD_LOGIC; -- VSYNC OUT
- vga_red_o : out STD_LOGIC_VECTOR (3 downto 0); -- Red signal going to the VGA interface
- vga_green_o : out STD_LOGIC_VECTOR (3 downto 0); -- Green signal going to the VGA interface
- vga_blue_o : out STD_LOGIC_VECTOR (3 downto 0) -- Blue signal going to the VGA interface
- );
-end sobelSys;
+entity sobelSys is
+ port (I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_go : in std_logic;
+ -- VGA Output Signals
+ O_vga_hs : out std_logic; -- HSYNC OUT
+ O_vga_vs : out std_logic; -- VSYNC OUT
+ O_vga_red : out std_logic_vector (3 downto 0); -- Red signal going to the VGA interface
+ O_vga_green : out std_logic_vector (3 downto 0); -- Green signal going to the VGA interface
+ O_vga_blue : out std_logic_vector (3 downto 0) -- Blue signal going to the VGA interface
+ );
+end sobelSys;
-architecture Behavioral of sobelSys is
+architecture Behavioral of sobelSys is
-- déclaration des sous-composants
- -- processeur Sobel
- component sobelProc is
- Port ( clk,reset : in STD_LOGIC;
- I_go : in STD_LOGIC;
- -- interface avec la mémoire IN (lecture)
- O_enM_R : out STD_LOGIC;
- O_ADR_R : out STD_LOGIC_VECTOR (13 downto 0);
- I_pixel : in STD_LOGIC_VECTOR (7 downto 0); -- Pixel from memory IN
- -- interface avec la mémoire OUT (écriture)
- O_enM_W : out STD_LOGIC;
- O_ADR_W : out STD_LOGIC_VECTOR (13 downto 0);
- O_pixEdge : out STD_LOGIC; -- Edge to memory OUT
- -- signal de commande vers le contrôleur VGA
- O_StartDisplay : out STD_LOGIC
- );
- end component sobelProc;
-
- -- Contrôleur VGA
- COMPONENT vga_nexys4_2regions
- PORT( clk_i : in STD_LOGIC;
- reset_i : in STD_LOGIC;
- -- VGA Output Signals
- vga_hs_o : out STD_LOGIC; -- HSYNC OUT
- vga_vs_o : out STD_LOGIC; -- VSYNC OUT
- vga_red_o : out STD_LOGIC_VECTOR (3 downto 0); -- Red signal going to the VGA interface
- vga_green_o : out STD_LOGIC_VECTOR (3 downto 0); -- Green signal going to the VGA interface
- vga_blue_o : out STD_LOGIC_VECTOR (3 downto 0); -- Blue signal going to the VGA interface
- ----------------------
- -- I/O internes, pour lire la mémoire de sortie de Sobel
- O_clk_25MHz : out STD_LOGIC;
- I_StartDisplay : in STD_LOGIC;
- ----
- O_enM_vga_region1 : out STD_LOGIC;
- O_addr_M_vga_region1 : out STD_LOGIC_VECTOR(13 downto 0);
- I_data_M_vga_region1 : in STD_LOGIC_VECTOR(7 downto 0);
- -----
- O_enM_vga_region2 : out STD_LOGIC;
- O_addr_M_vga_region2 : out STD_LOGIC_VECTOR(13 downto 0);
- I_data_M_vga_region2 : in STD_LOGIC_VECTOR(7 downto 0)
- );
- END COMPONENT;
-
- -- Mémoire d'entrée
- component SinglePortROMFileInitGeneric is
- generic (
- G_MemoryWidth : Integer;
- G_MemoryDepth : Integer;
- G_AddressWidth : Integer;
- G_InitFileName : String
+ -- processeur Sobel
+ component sobelProc is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic; I_go : in std_logic;
+ -- interface avec la mémoire IN (lecture)
+ O_enM_R : out std_logic;
+ O_ADR_R : out std_logic_vector (13 downto 0);
+ I_pixel : in std_logic_vector (7 downto 0); -- Pixel from memory IN
+ -- interface avec la mémoire OUT (écriture)
+ O_enM_W : out std_logic;
+ O_ADR_W : out std_logic_vector (13 downto 0);
+ O_pixEdge : out std_logic; -- Edge to memory OUT
+ -- signal de commande vers le contrôleur VGA
+ O_StartDisplay : out std_logic
);
- port (
- I_clk : In std_logic;
- I_en : In std_logic;
- I_addr : In std_logic_vector(G_AddressWidth - 1 Downto 0);
- O_dout : Out std_logic_vector(G_MemoryWidth - 1 Downto 0)
- );
- end component;
-
- -- Mémoire de sortie
- component DualPortRamGeneric is
- generic (
- G_MemoryWidth : Integer;
- G_MemoryDepth : Integer;
- G_AddressWidth : Integer
- );
- port (
- I_clk : in std_logic;
- I_ena : in std_logic;
- I_enb : in std_logic;
- I_wea : in std_logic;
- I_addra : in std_logic_vector(G_AddressWidth-1 downto 0);
- I_addrb : in std_logic_vector(G_AddressWidth-1 downto 0);
- I_dina : in std_logic_vector(G_MemoryWidth-1 downto 0);
- O_douta : out std_logic_vector(G_MemoryWidth-1 downto 0);
- O_doutb : out std_logic_vector(G_MemoryWidth-1 downto 0)
- );
- end component;
-
--- déclaration des signaux internes
-signal S_clk_25MHz : std_logic;
-signal S_StartDisplay : std_logic;
-signal reset_h : std_logic;
+ end component sobelProc;
+
+ -- Contrôleur VGA
+ component vga_nexys4_2regions
+ port(
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ -- VGA Output Signals
+ vga_hs_o : out std_logic; -- HSYNC OUT
+ vga_vs_o : out std_logic; -- VSYNC OUT
+ vga_red_o : out std_logic_vector (3 downto 0); -- Red signal going to the VGA interface
+ vga_green_o : out std_logic_vector (3 downto 0); -- Green signal going to the VGA interface
+ vga_blue_o : out std_logic_vector (3 downto 0); -- Blue signal going to the VGA interface
+ ----------------------
+ -- I/O internes, pour lire la mémoire de sortie de Sobel
+ O_clk_25MHz : out std_logic;
+ I_StartDisplay : in std_logic;
+ ----
+ O_enM_vga_region1 : out std_logic;
+ O_addr_M_vga_region1 : out std_logic_vector(13 downto 0);
+ I_data_M_vga_region1 : in std_logic_vector(7 downto 0);
+ -----
+ O_enM_vga_region2 : out std_logic;
+ O_addr_M_vga_region2 : out std_logic_vector(13 downto 0);
+ I_data_M_vga_region2 : in std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ -- Mémoire d'entrée
+ component SinglePortROMFileInitGeneric is
+ generic (
+ G_MemoryWidth : integer;
+ G_MemoryDepth : integer;
+ G_AddressWidth : integer;
+ G_InitFileName : string
+ );
+ port (
+ I_clk : in std_logic;
+ I_en : in std_logic;
+ I_addr : in std_logic_vector(G_AddressWidth - 1 downto 0);
+ O_dout : out std_logic_vector(G_MemoryWidth - 1 downto 0)
+ );
+ end component;
+
+ -- Mémoire de sortie
+ component DualPortRamGeneric is
+ generic (
+ G_MemoryWidth : integer;
+ G_MemoryDepth : integer;
+ G_AddressWidth : integer
+ );
+ port (
+ I_clk : in std_logic;
+ I_ena : in std_logic;
+ I_enb : in std_logic;
+ I_wea : in std_logic;
+ I_addra : in std_logic_vector(G_AddressWidth-1 downto 0);
+ I_addrb : in std_logic_vector(G_AddressWidth-1 downto 0);
+ I_dina : in std_logic_vector(G_MemoryWidth-1 downto 0);
+ O_douta : out std_logic_vector(G_MemoryWidth-1 downto 0);
+ O_doutb : out std_logic_vector(G_MemoryWidth-1 downto 0)
+ );
+ end component;
+-- déclaration des signaux internes
+ signal S_clk_25MHz : std_logic;
+ signal S_StartDisplay : std_logic;
+ signal reset_h : std_logic;
-signal S_enM_R : std_logic;
-signal S_addr_R : std_logic_vector(13 Downto 0);
-signal S_Pixel : std_logic_vector(7 Downto 0);
+ signal S_enM_R : std_logic;
+ signal S_addr_R : std_logic_vector(13 downto 0);
+ signal S_Pixel : std_logic_vector(7 downto 0);
-signal S_enM_W : std_logic;
-signal S_addr_W : std_logic_vector(13 Downto 0);
-signal S_PixEdge_1bit : std_logic;
-signal S_PixEdge_8bits : std_logic_vector(7 Downto 0);
+ signal S_enM_W : std_logic;
+ signal S_addr_W : std_logic_vector(13 downto 0);
+ signal S_PixEdge_1bit : std_logic;
+ signal S_PixEdge_8bits : std_logic_vector(7 downto 0);
-signal S_enM_vga_region1 : std_logic;
-signal S_addr_M_vga_region1 : std_logic_vector(13 Downto 0);
-signal S_data_M_vga_region1 : std_logic_vector(7 Downto 0);
+ signal S_enM_vga_region1 : std_logic;
+ signal S_addr_M_vga_region1 : std_logic_vector(13 downto 0);
+ signal S_data_M_vga_region1 : std_logic_vector(7 downto 0);
-signal S_enM_vga_region2 : std_logic;
-signal S_addr_M_vga_region2 : std_logic_vector(13 Downto 0);
-signal S_data_M_vga_region2 : std_logic_vector(7 Downto 0);
-
-signal S_mux_enM_R : std_logic;
-signal S_mux_ADR_R : std_logic_vector(13 Downto 0);
+ signal S_enM_vga_region2 : std_logic;
+ signal S_addr_M_vga_region2 : std_logic_vector(13 downto 0);
+ signal S_data_M_vga_region2 : std_logic_vector(7 downto 0);
-signal s_douta_not_used : std_logic_vector(7 Downto 0);
+ signal S_mux_enM_R : std_logic;
+ signal S_mux_ADR_R : std_logic_vector(13 downto 0);
+ signal s_douta_not_used : std_logic_vector(7 downto 0);
begin
-S_PixEdge_8bits <= S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit;
+ S_PixEdge_8bits <= S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit&S_PixEdge_1bit;
-- instanciation des sous-composants et établissement des interconnexions
-reset_h <= not reset_i;
-
-S_mux_ADR_R <= S_addr_R when S_StartDisplay = '0' else S_addr_M_vga_region1;
-S_mux_enM_R <= S_enM_R when S_StartDisplay = '0' else S_enM_vga_region1;
-S_data_M_vga_region1 <= S_Pixel;
-
- -- instanciation du processeur Sobel
- sobelProc_inst1 : entity work.sobelProc
- port map (
- clk => S_clk_25MHz,
- reset => reset_h,
- I_go => go_i,
- O_enM_R => S_enM_R,
- O_ADR_R => S_addr_R,
- I_pixel => S_Pixel,
- O_enM_W => S_enM_W,
- O_ADR_W => S_addr_W,
- O_pixEdge => S_PixEdge_1bit,
- O_StartDisplay => S_StartDisplay
- );
-
- -- instanciation du contrôleur VGA
- vga_inst1 : vga_nexys4_2regions
- port map (
- clk_i => clk_i ,
- reset_i => reset_h ,
- vga_hs_o => vga_hs_o ,
- vga_vs_o => vga_vs_o ,
- vga_red_o => vga_red_o ,
- vga_green_o => vga_green_o ,
- vga_blue_o => vga_blue_o ,
- O_clk_25MHz => S_clk_25MHz ,
- I_StartDisplay => S_StartDisplay ,
- O_enM_vga_region1 => S_enM_vga_region1 ,
- O_addr_M_vga_region1 => S_addr_M_vga_region1 ,
- I_data_M_vga_region1 => S_data_M_vga_region1 ,
- O_enM_vga_region2 => S_enM_vga_region2 ,
- O_addr_M_vga_region2 => S_addr_M_vga_region2 ,
- I_data_M_vga_region2 => S_data_M_vga_region2
- );
-
- -- instanciation de la mémoire d'entrée
- rom_in : SinglePortROMFileInitGeneric
- generic map (
- G_MemoryWidth => 8,
- G_MemoryDepth => 10000,
- G_AddressWidth => 14,
- G_InitFileName => "dancing_spider.txt"
- )
- port map (
- I_clk => S_clk_25MHz,
- I_en => S_mux_enM_R,
- I_addr => S_mux_ADR_R,
- O_dout => S_Pixel
- );
-
-
- -- instanciation de la mémoire de sortie
- ram_out : DualPortRamGeneric
- generic map (
- G_MemoryWidth => 8,
- G_MemoryDepth => 10000,
- G_AddressWidth => 14
- )
- port map (
- I_clk => S_clk_25MHz,
- I_ena => S_enM_W,
- I_enb => S_enM_vga_region2,
- I_wea => S_enM_W,
- I_addra => S_addr_W,
- I_addrb => S_addr_M_vga_region2,
- I_dina => S_PixEdge_8bits,
- O_douta => s_douta_not_used,
- O_doutb => S_data_M_vga_region2
- );
-
-
-
-end Behavioral;
+ reset_h <= not I_rst;
+
+ S_mux_ADR_R <= S_addr_R when S_StartDisplay = '0' else S_addr_M_vga_region1;
+ S_mux_enM_R <= S_enM_R when S_StartDisplay = '0' else S_enM_vga_region1;
+ S_data_M_vga_region1 <= S_Pixel;
+
+ -- instanciation du processeur Sobel
+ sobelProc_inst1 : entity work.sobelProc
+ port map (
+ I_clk => S_clk_25MHz,
+ I_rst => reset_h,
+ I_go => I_go,
+ O_enM_R => S_enM_R,
+ O_ADR_R => S_addr_R,
+ I_pixel => S_Pixel,
+ O_enM_W => S_enM_W,
+ O_ADR_W => S_addr_W,
+ O_pixEdge => S_PixEdge_1bit,
+ O_StartDisplay => S_StartDisplay
+ );
+ -- instanciation du contrôleur VGA
+ vga_inst1 : vga_nexys4_2regions
+ port map (
+ clk_i => I_clk,
+ reset_i => reset_h,
+ vga_hs_o => O_vga_hs,
+ vga_vs_o => O_vga_vs,
+ vga_red_o => O_vga_red,
+ vga_green_o => O_vga_green,
+ vga_blue_o => O_vga_blue,
+ O_clk_25MHz => S_clk_25MHz,
+ I_StartDisplay => S_StartDisplay,
+ O_enM_vga_region1 => S_enM_vga_region1,
+ O_addr_M_vga_region1 => S_addr_M_vga_region1,
+ I_data_M_vga_region1 => S_data_M_vga_region1,
+ O_enM_vga_region2 => S_enM_vga_region2,
+ O_addr_M_vga_region2 => S_addr_M_vga_region2,
+ I_data_M_vga_region2 => S_data_M_vga_region2
+ );
+
+ -- instanciation de la mémoire d'entrée
+ rom_in : SinglePortROMFileInitGeneric
+ generic map (
+ G_MemoryWidth => 8,
+ G_MemoryDepth => 10000,
+ G_AddressWidth => 14,
+ G_InitFileName => "dancing_spider.txt"
+ )
+ port map (
+ I_clk => S_clk_25MHz,
+ I_en => S_mux_enM_R,
+ I_addr => S_mux_ADR_R,
+ O_dout => S_Pixel
+ );
+
+
+ -- instanciation de la mémoire de sortie
+ ram_out : DualPortRamGeneric
+ generic map (
+ G_MemoryWidth => 8,
+ G_MemoryDepth => 10000,
+ G_AddressWidth => 14
+ )
+ port map (
+ I_clk => S_clk_25MHz,
+ I_ena => S_enM_W,
+ I_enb => S_enM_vga_region2,
+ I_wea => S_enM_W,
+ I_addra => S_addr_W,
+ I_addrb => S_addr_M_vga_region2,
+ I_dina => S_PixEdge_8bits,
+ O_douta => s_douta_not_used,
+ O_doutb => S_data_M_vga_region2
+ );
+
+end Behavioral;
diff --git a/src/tb_adrgenUnit.vhd b/src/tb_adrgenUnit.vhd
index fd1bea3..540852c 100644
--- a/src/tb_adrgenUnit.vhd
+++ b/src/tb_adrgenUnit.vhd
@@ -7,81 +7,77 @@ entity tb_adrgenUnit is
end entity tb_adrgenUnit;
architecture archi_tb_adrgenUnit of tb_adrgenUnit is
-
- signal S_clk : std_logic := '1';
- signal S_reset : std_logic := '1';
- signal S_clr_PtrLine : STD_LOGIC := '0';
- signal S_inc_PtrLine : STD_LOGIC := '0';
- signal S_clr_PtrCol : STD_LOGIC := '0';
- signal S_inc_PtrCol : STD_LOGIC := '0';
- signal S_selPix : STD_LOGIC_VECTOR (1 downto 0) := "00";
- signal S_EndImage : STD_LOGIC;
- signal S_NewLine : STD_LOGIC;
- signal S_ADR_R : STD_LOGIC_VECTOR (13 downto 0);
- signal S_ADR_W : STD_LOGIC_VECTOR (13 downto 0);
- constant clk_period : time := 10 ns;
+ signal S_clk : std_logic := '1';
+ signal S_clr_PtrLine : std_logic := '0';
+ signal S_inc_PtrLine : std_logic := '0';
+ signal S_clr_PtrCol : std_logic := '0';
+ signal S_inc_PtrCol : std_logic := '0';
+ signal S_selPix : std_logic_vector (1 downto 0) := "00";
+ signal S_EndImage : std_logic;
+ signal S_NewLine : std_logic;
+ signal S_ADR_R : std_logic_vector (13 downto 0);
+ signal S_ADR_W : std_logic_vector (13 downto 0);
+
+ constant clk_period : time := 10 ns;
begin
- S_clk <= not S_clk after clk_period/2;
- S_reset <= '1', '0' after 2*clk_period;
- S_clr_PtrLine <= '1', '0' after 2*clk_period;
- S_clr_PtrCol <= '1', '0' after 2*clk_period;
-
+ S_clk <= not S_clk after clk_period/2;
+ S_clr_PtrLine <= '1', '0' after 2*clk_period;
+ S_clr_PtrCol <= '1', '0' after 2*clk_period;
+
+
+ process
+ begin
+ wait for 2*clk_period;
+ while true loop
+ S_selPix <= "00";
+ wait for clk_period;
+ S_selPix <= "01";
+ wait for clk_period;
+ S_selPix <= "10";
+ wait for clk_period;
+ wait for clk_period; -- pour le "shift" des registres
+ end loop;
+ end process;
+
+ process
+ begin
+ wait for 2*clk_period;
+ while true loop
+ wait for 3*clk_period;
+ S_inc_PtrCol <= '1';
+ wait for clk_period;
+ S_inc_PtrCol <= '0';
+ end loop;
+ end process;
+
+ process
+ begin
+ wait for 2*clk_period;
+ while true loop
+ wait for (4*clk_period*100 - clk_period); -- 40 ns x 100 - 10 ns
+ S_inc_PtrLine <= '1';
+ wait for clk_period;
+ S_inc_PtrLine <= '0';
+ end loop;
+ end process;
- process
- begin
- wait for 2*clk_period;
- while true loop
- S_selPix <= "00";
- wait for clk_period;
- S_selPix <= "01";
- wait for clk_period;
- S_selPix <= "10";
- wait for clk_period;
- wait for clk_period; -- pour le "shift" des registres
- end loop;
- end process;
-
- process
- begin
- wait for 2*clk_period;
- while true loop
- wait for 3*clk_period;
- S_inc_PtrCol <= '1';
- wait for clk_period;
- S_inc_PtrCol <= '0';
- end loop;
- end process;
- process
- begin
- --wait until S_reset = '0';
- wait for 2*clk_period;
- while true loop
- wait for (4*clk_period*100 - clk_period); -- 40 ns x 100 - 10 ns
- S_inc_PtrLine <= '1';
- wait for clk_period;
- S_inc_PtrLine <= '0';
- end loop;
- end process;
-
-
- adrgenUnit_1 : entity work.adrgenUnit
- port map (
- clk => S_clk,
- reset => S_reset,
- I_clr_PtrLine => S_clr_PtrLine,
- I_inc_PtrLine => S_inc_PtrLine,
- I_clr_PtrCol => S_clr_PtrCol,
- I_inc_PtrCol => S_inc_PtrCol,
- I_selPix => S_selPix,
- O_EndImage => S_EndImage,
- O_NewLine => S_NewLine,
- O_ADR_R => S_ADR_R,
- O_ADR_W => S_ADR_W
- );
+ adrgenUnit_1 : entity work.adrgenUnit
+ port map (
+ I_clk => S_clk,
+ I_clr_PtrLine => S_clr_PtrLine,
+ I_inc_PtrLine => S_inc_PtrLine,
+ I_clr_PtrCol => S_clr_PtrCol,
+ I_inc_PtrCol => S_inc_PtrCol,
+ I_selPix => S_selPix,
+ O_EndImage => S_EndImage,
+ O_NewLine => S_NewLine,
+ O_ADR_R => S_ADR_R,
+ O_ADR_W => S_ADR_W
+ );
end architecture archi_tb_adrgenUnit;
diff --git a/src/tb_automate.vhd b/src/tb_automate.vhd
index 228df48..fbb9c62 100644
--- a/src/tb_automate.vhd
+++ b/src/tb_automate.vhd
@@ -7,68 +7,68 @@ entity tb_automate is
end entity tb_automate;
architecture archi_tb_automate of tb_automate is
-
- signal S_clk : STD_LOGIC := '1';
- signal S_reset : STD_LOGIC := '1';
- signal S_go : STD_LOGIC := '0';
- signal S_EndImage : STD_LOGIC := '0';
- signal S_NewLine : STD_LOGIC := '0';
- signal S_ldPix11 : STD_LOGIC;
- signal S_ldPix21 : STD_LOGIC;
- signal S_ldPix31 : STD_LOGIC;
- signal S_shReg : STD_LOGIC;
- signal S_ldPixEdge : STD_LOGIC;
- signal S_clr_PtrLine : STD_LOGIC;
- signal S_inc_PtrLine : STD_LOGIC;
- signal S_clr_PtrCol : STD_LOGIC;
- signal S_inc_PtrCol : STD_LOGIC;
- signal S_selPix : STD_LOGIC_VECTOR (1 downto 0);
- signal S_enM_R : STD_LOGIC;
- signal S_enM_W : STD_LOGIC;
- signal S_StartDisplay : STD_LOGIC;
- constant clk_period : time := 10 ns;
+ signal S_clk : std_logic := '1';
+ signal S_reset : std_logic := '1';
+ signal S_go : std_logic := '0';
+ signal S_EndImage : std_logic := '0';
+ signal S_NewLine : std_logic := '0';
+ signal S_ldPix11 : std_logic;
+ signal S_ldPix21 : std_logic;
+ signal S_ldPix31 : std_logic;
+ signal S_shReg : std_logic;
+ signal S_ldPixEdge : std_logic;
+ signal S_clr_PtrLine : std_logic;
+ signal S_inc_PtrLine : std_logic;
+ signal S_clr_PtrCol : std_logic;
+ signal S_inc_PtrCol : std_logic;
+ signal S_selPix : std_logic_vector (1 downto 0);
+ signal S_enM_R : std_logic;
+ signal S_enM_W : std_logic;
+ signal S_StartDisplay : std_logic;
+
+ constant clk_period : time := 10 ns;
begin
- S_clk <= not S_clk after clk_period/2;
- S_reset <= '1', '0' after 2*clk_period;
- S_go <= '0', '1' after 4*clk_period, '0' after 5*clk_period;
+ S_clk <= not S_clk after clk_period/2;
+ S_reset <= '1', '0' after 2*clk_period;
+ S_go <= '0', '1' after 4*clk_period, '0' after 5*clk_period;
+
+ process
+ begin
+ S_NewLine <= '0';
+ wait for 4*clk_period; -- wait for go = '1'
+ wait for (2 + 13)*clk_period; -- traitement du 1er pixel
+ wait for (2*6)*clk_period; -- traitement de 2 pixels suivants (pas besoin de répéter 100 fois pour ce testbench)
+ S_NewLine <= '1';
+ wait for clk_period;
+ S_NewLine <= '0';
+ end process;
+
+ S_EndImage <= '0', '1' after 100*clk_period; -- just pour tester le passage à l'état final EndSobel
+
+
+ automate_1 : entity work.automate
+ port map (
+ I_clk => S_clk,
+ I_rst => S_reset,
+ I_go => S_go,
+ I_EndImage => S_EndImage,
+ I_NewLine => S_NewLine,
+ O_ldPix11 => S_ldPix11,
+ O_ldPix21 => S_ldPix21,
+ O_ldPix31 => S_ldPix31,
+ O_shReg => S_shReg,
+ O_ldPixEdge => S_ldPixEdge,
+ O_clr_PtrLine => S_clr_PtrLine,
+ O_inc_PtrLine => S_inc_PtrLine,
+ O_clr_PtrCol => S_clr_PtrCol,
+ O_inc_PtrCol => S_inc_PtrCol,
+ O_selPix => S_selPix,
+ O_enM_R => S_enM_R,
+ O_enM_W => S_enM_W,
+ O_StartDisplay => S_StartDisplay
+ );
- process
- begin
- S_NewLine <= '0';
- wait for 4*clk_period; -- wait for go = '1'
- wait for (2 + 13)*clk_period; -- traitement du 1er pixel
- wait for (2*6)*clk_period; -- traitement de 2 pixels suivants (pas besoin de répéter 100 fois pour ce testbench)
- S_NewLine <= '1';
- wait for clk_period;
- S_NewLine <= '0';
- end process;
-
- S_EndImage <= '0', '1' after 100*clk_period; -- just pour tester le passage à l'état final EndSobel
-
-
- automate_1 : entity work.automate
- port map (
- clk => S_clk,
- reset => S_reset,
- I_go => S_go,
- I_EndImage => S_EndImage,
- I_NewLine => S_NewLine,
- O_ldPix11 => S_ldPix11,
- O_ldPix21 => S_ldPix21,
- O_ldPix31 => S_ldPix31,
- O_shReg => S_shReg,
- O_ldPixEdge => S_ldPixEdge,
- O_clr_PtrLine => S_clr_PtrLine,
- O_inc_PtrLine => S_inc_PtrLine,
- O_clr_PtrCol => S_clr_PtrCol,
- O_inc_PtrCol => S_inc_PtrCol,
- O_selPix => S_selPix,
- O_enM_R => S_enM_R,
- O_enM_W => S_enM_W,
- O_StartDisplay => S_StartDisplay
- );
-
end architecture archi_tb_automate;
diff --git a/src/tb_gradientUnit.vhd b/src/tb_gradientUnit.vhd
index 7d0fe35..1eaba33 100644
--- a/src/tb_gradientUnit.vhd
+++ b/src/tb_gradientUnit.vhd
@@ -7,48 +7,47 @@ entity tb_gradientUnit is
end entity tb_gradientUnit;
architecture archi_tb_gradientUnit of tb_gradientUnit is
- component gradientUnit is
- port ( I_Pix11, I_Pix12, I_Pix13 : in STD_LOGIC_VECTOR (7 downto 0);
- I_Pix21, I_Pix22, I_Pix23 : in STD_LOGIC_VECTOR (7 downto 0);
- I_Pix31, I_Pix32, I_Pix33 : in STD_LOGIC_VECTOR (7 downto 0);
- O_pixEdge : out STD_LOGIC
- );
- end component gradientUnit;
- signal S_pixEdge : std_logic;
- signal S_Pix11, S_Pix12, S_Pix13 : STD_LOGIC_VECTOR (7 downto 0);
- signal S_Pix21, S_Pix22, S_Pix23 : STD_LOGIC_VECTOR (7 downto 0);
- signal S_Pix31, S_Pix32, S_Pix33 : STD_LOGIC_VECTOR (7 downto 0);
+ component gradientUnit is
+ port (
+ I_Pix11, I_Pix12, I_Pix13 : in std_logic_vector (7 downto 0);
+ I_Pix21, I_Pix22, I_Pix23 : in std_logic_vector (7 downto 0);
+ I_Pix31, I_Pix32, I_Pix33 : in std_logic_vector (7 downto 0);
+ O_pixEdge : out std_logic
+ );
+ end component gradientUnit;
+ signal S_pixEdge : std_logic;
+ signal S_Pix11, S_Pix12, S_Pix13 : std_logic_vector (7 downto 0);
+ signal S_Pix21, S_Pix22, S_Pix23 : std_logic_vector (7 downto 0);
+ signal S_Pix31, S_Pix32, S_Pix33 : std_logic_vector (7 downto 0);
begin
-
- S_Pix11 <= STD_LOGIC_VECTOR(to_unsigned(15,8)) , STD_LOGIC_VECTOR(to_unsigned(15,8)) after 200 ns;
- S_Pix12 <= STD_LOGIC_VECTOR(to_unsigned(15,8)) , STD_LOGIC_VECTOR(to_unsigned(15,8)) after 200 ns;
- S_Pix13 <= STD_LOGIC_VECTOR(to_unsigned(15,8)) , STD_LOGIC_VECTOR(to_unsigned(15,8)) after 200 ns;
-
- S_Pix21 <= STD_LOGIC_VECTOR(to_unsigned(80,8)) , STD_LOGIC_VECTOR(to_unsigned(15,8)) after 200 ns;
- S_Pix22 <= STD_LOGIC_VECTOR(to_unsigned(80,8)) , STD_LOGIC_VECTOR(to_unsigned(15,8)) after 200 ns;
- S_Pix23 <= STD_LOGIC_VECTOR(to_unsigned(80,8)) , STD_LOGIC_VECTOR(to_unsigned(15,8)) after 200 ns;
-
- S_Pix31 <= STD_LOGIC_VECTOR(to_unsigned(150,8)) , STD_LOGIC_VECTOR(to_unsigned(15,8)) after 200 ns;
- S_Pix32 <= STD_LOGIC_VECTOR(to_unsigned(150,8)) , STD_LOGIC_VECTOR(to_unsigned(15,8)) after 200 ns;
- S_Pix33 <= STD_LOGIC_VECTOR(to_unsigned(150,8)) , STD_LOGIC_VECTOR(to_unsigned(15,8)) after 200 ns;
-
-
- gradientUnit_1 : entity work.gradientUnit
- port map (
- O_pixEdge => S_pixEdge,
- I_Pix11 => S_Pix11,
- I_Pix12 => S_Pix12,
- I_Pix13 => S_Pix13,
- I_Pix21 => S_Pix21,
- I_Pix22 => S_Pix22,
- I_Pix23 => S_Pix23,
- I_Pix31 => S_Pix31,
- I_Pix32 => S_Pix32,
- I_Pix33 => S_Pix33);
-
+ S_Pix11 <= std_logic_vector(to_unsigned(15, 8)), std_logic_vector(to_unsigned(15, 8)) after 200 ns;
+ S_Pix12 <= std_logic_vector(to_unsigned(15, 8)), std_logic_vector(to_unsigned(15, 8)) after 200 ns;
+ S_Pix13 <= std_logic_vector(to_unsigned(15, 8)), std_logic_vector(to_unsigned(15, 8)) after 200 ns;
+
+ S_Pix21 <= std_logic_vector(to_unsigned(80, 8)), std_logic_vector(to_unsigned(15, 8)) after 200 ns;
+ S_Pix22 <= std_logic_vector(to_unsigned(80, 8)), std_logic_vector(to_unsigned(15, 8)) after 200 ns;
+ S_Pix23 <= std_logic_vector(to_unsigned(80, 8)), std_logic_vector(to_unsigned(15, 8)) after 200 ns;
+
+ S_Pix31 <= std_logic_vector(to_unsigned(150, 8)), std_logic_vector(to_unsigned(15, 8)) after 200 ns;
+ S_Pix32 <= std_logic_vector(to_unsigned(150, 8)), std_logic_vector(to_unsigned(15, 8)) after 200 ns;
+ S_Pix33 <= std_logic_vector(to_unsigned(150, 8)), std_logic_vector(to_unsigned(15, 8)) after 200 ns;
+
+ gradientUnit_1 : entity work.gradientUnit
+ port map (
+ O_pixEdge => S_pixEdge,
+ I_Pix11 => S_Pix11,
+ I_Pix12 => S_Pix12,
+ I_Pix13 => S_Pix13,
+ I_Pix21 => S_Pix21,
+ I_Pix22 => S_Pix22,
+ I_Pix23 => S_Pix23,
+ I_Pix31 => S_Pix31,
+ I_Pix32 => S_Pix32,
+ I_Pix33 => S_Pix33
+ );
end architecture archi_tb_gradientUnit;
diff --git a/src/tb_operativeUnit.vhd b/src/tb_operativeUnit.vhd
index 0f7ff99..a5aa0b1 100644
--- a/src/tb_operativeUnit.vhd
+++ b/src/tb_operativeUnit.vhd
@@ -7,66 +7,55 @@ entity tb_operativeUnit is
end entity tb_operativeUnit;
architecture archi_tb_operativeUnit of tb_operativeUnit is
- component operativeUnit is
- Port ( clk :in STD_LOGIC;
- reset :in STD_LOGIC;
- I_pixel : in STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
- I_ldPix11 : in STD_LOGIC;
- I_ldPix21 : in STD_LOGIC;
- I_ldPix31 : in STD_LOGIC;
- I_shReg : in STD_LOGIC;
- I_ldPixEdge : in STD_LOGIC;
- O_pixEdge : out STD_LOGIC
- );
- end component operativeUnit;
- signal S_clk : std_logic := '0';
- signal S_reset : std_logic;
- signal S_pixel : STD_LOGIC_VECTOR (7 downto 0);
- signal S_ldPix11 : std_logic;
- signal S_ldPix21 : std_logic;
- signal S_ldPix31 : std_logic;
- signal S_shReg : std_logic;
- signal S_ldPixEdge : std_logic;
- signal S_pixEdge : std_logic;
+ component operativeUnit is
+ port (I_clk : in std_logic;
+ I_pixel : in std_logic_vector (7 downto 0); -- Pixel from the memory
+ I_ldPix11 : in std_logic;
+ I_ldPix21 : in std_logic;
+ I_ldPix31 : in std_logic;
+ I_shReg : in std_logic;
+ I_ldPixEdge : in std_logic;
+ O_pixEdge : out std_logic
+ );
+ end component operativeUnit;
+
+ signal S_I_clk : std_logic := '0';
+ signal S_pixel : std_logic_vector (7 downto 0):= (others => '0');
+ signal S_ldPix11 : std_logic;
+ signal S_ldPix21 : std_logic;
+ signal S_ldPix31 : std_logic;
+ signal S_shReg : std_logic;
+ signal S_ldPixEdge : std_logic;
+ signal S_pixEdge : std_logic;
begin
- S_clk <= not S_clk after 5 ns;
- S_reset <= '0', '1' after 23 ns, '0' after 64 ns;
-
- S_ldPix11 <= '0', '1' after 102 ns, '0' after 112 ns, '1' after 142 ns, '0' after 152 ns, '1' after 182 ns, '0' after 192 ns, '1' after 222 ns, '0' after 232 ns;
-
- S_ldPix21 <= '0', '1' after 112 ns, '0' after 122 ns, '1' after 152 ns, '0' after 162 ns, '1' after 192 ns, '0' after 202 ns, '1' after 232 ns, '0' after 242 ns;
-
- S_ldPix31 <= '0', '1' after 122 ns, '0' after 132 ns, '1' after 162 ns, '0' after 172 ns, '1' after 202 ns, '0' after 212 ns, '1' after 242 ns, '0' after 252 ns;
-
- S_shReg <= '0', '1' after 132 ns, '0' after 142 ns, '1' after 172 ns, '0' after 182 ns, '1' after 212 ns, '0' after 222 ns, '1' after 252 ns, '0' after 262 ns;
-
- S_ldPixEdge <= '0', '1' after 212 ns, '0' after 222 ns, '1' after 252 ns, '0' after 262 ns;
-
- process (S_clk, s_reset)
- begin
- if s_reset = '1' then
- S_pixel <= (others => '0');
- elsif (rising_edge(S_clk)) then
- S_pixel <= STD_LOGIC_VECTOR(unsigned(S_pixel) + 1);
- end if;
- end process;
-
-
- operativeUnit_1 : entity work.operativeUnit
- port map (
- clk => S_clk,
- reset => S_reset,
- I_pixel => S_pixel,
- I_ldPix11 => S_ldPix11,
- I_ldPix21 => S_ldPix21,
- I_ldPix31 => S_ldPix31,
- I_shReg => S_shReg,
- I_ldPixEdge => S_ldPixEdge,
- O_pixEdge => S_pixEdge
- );
-
+ S_I_clk <= not S_I_clk after 5 ns;
+ S_ldPix11 <= '0', '1' after 102 ns, '0' after 112 ns, '1' after 142 ns, '0' after 152 ns, '1' after 182 ns, '0' after 192 ns, '1' after 222 ns, '0' after 232 ns;
+ S_ldPix21 <= '0', '1' after 112 ns, '0' after 122 ns, '1' after 152 ns, '0' after 162 ns, '1' after 192 ns, '0' after 202 ns, '1' after 232 ns, '0' after 242 ns;
+ S_ldPix31 <= '0', '1' after 122 ns, '0' after 132 ns, '1' after 162 ns, '0' after 172 ns, '1' after 202 ns, '0' after 212 ns, '1' after 242 ns, '0' after 252 ns;
+ S_shReg <= '0', '1' after 132 ns, '0' after 142 ns, '1' after 172 ns, '0' after 182 ns, '1' after 212 ns, '0' after 222 ns, '1' after 252 ns, '0' after 262 ns;
+ S_ldPixEdge <= '0', '1' after 212 ns, '0' after 222 ns, '1' after 252 ns, '0' after 262 ns;
+
+ process (S_I_clk)
+ begin
+ if(rising_edge(S_I_clk)) then
+ S_pixel <= std_logic_vector(unsigned(S_pixel) + 1);
+ end if;
+ end process;
+
+
+ operativeUnit_1 : entity work.operativeUnit
+ port map (
+ I_clk => S_I_clk,
+ I_pixel => S_pixel,
+ I_ldPix11 => S_ldPix11,
+ I_ldPix21 => S_ldPix21,
+ I_ldPix31 => S_ldPix31,
+ I_shReg => S_shReg,
+ I_ldPixEdge => S_ldPixEdge,
+ O_pixEdge => S_pixEdge
+ );
end architecture archi_tb_operativeUnit;
diff --git a/src/tb_regUnit.vhd b/src/tb_regUnit.vhd
index 5cee612..a09ee8b 100644
--- a/src/tb_regUnit.vhd
+++ b/src/tb_regUnit.vhd
@@ -7,73 +7,63 @@ entity tb_regUnit is
end entity tb_regUnit;
architecture archi_tb_regUnit of tb_regUnit is
- component regUnit is
- port (clk,reset :in STD_LOGIC;
- I_pixel : in STD_LOGIC_VECTOR (7 downto 0); -- Pixel from the memory
- I_ldPix11 : in STD_LOGIC;
- I_ldPix21 : in STD_LOGIC;
- I_ldPix31 : in STD_LOGIC;
- I_shReg : in STD_LOGIC;
- O_Pix11, O_Pix12, O_Pix13 : out STD_LOGIC_VECTOR (7 downto 0);
- O_Pix21, O_Pix22, O_Pix23 : out STD_LOGIC_VECTOR (7 downto 0);
- O_Pix31, O_Pix32, O_Pix33 : out STD_LOGIC_VECTOR (7 downto 0)
- );
- end component regUnit;
- signal S_clk : std_logic := '0';
- signal S_reset : std_logic;
- signal S_pixel : STD_LOGIC_VECTOR (7 downto 0);
- signal S_ldPix11 : std_logic;
- signal S_ldPix21 : std_logic;
- signal S_ldPix31 : std_logic;
- signal S_shReg : std_logic;
- signal S_Pix11, S_Pix12, S_Pix13 : STD_LOGIC_VECTOR (7 downto 0);
- signal S_Pix21, S_Pix22, S_Pix23 : STD_LOGIC_VECTOR (7 downto 0);
- signal S_Pix31, S_Pix32, S_Pix33 : STD_LOGIC_VECTOR (7 downto 0);
+ component regUnit is
+ port (I_clk : in std_logic;
+ I_pixel : in std_logic_vector (7 downto 0); -- Pixel from the memory
+ I_ldPix11 : in std_logic;
+ I_ldPix21 : in std_logic;
+ I_ldPix31 : in std_logic;
+ I_shReg : in std_logic;
+ O_Pix11, O_Pix12, O_Pix13 : out std_logic_vector (7 downto 0);
+ O_Pix21, O_Pix22, O_Pix23 : out std_logic_vector (7 downto 0);
+ O_Pix31, O_Pix32, O_Pix33 : out std_logic_vector (7 downto 0)
+ );
+ end component regUnit;
+ signal S_clk : std_logic := '0';
+ signal S_pixel : std_logic_vector (7 downto 0) := (others => '0');
+ signal S_ldPix11 : std_logic;
+ signal S_ldPix21 : std_logic;
+ signal S_ldPix31 : std_logic;
+ signal S_shReg : std_logic;
+ signal S_Pix11, S_Pix12, S_Pix13 : std_logic_vector (7 downto 0);
+ signal S_Pix21, S_Pix22, S_Pix23 : std_logic_vector (7 downto 0);
+ signal S_Pix31, S_Pix32, S_Pix33 : std_logic_vector (7 downto 0);
begin
- S_clk <= not S_clk after 5 ns;
- S_reset <= '0', '1' after 23 ns, '0' after 64 ns;
+ S_clk <= not S_clk after 5 ns;
- S_ldPix11 <= '0', '1' after 102 ns, '0' after 112 ns, '1' after 142 ns, '0' after 152 ns, '1' after 182 ns, '0' after 192 ns, '1' after 222 ns, '0' after 232 ns;
-
- S_ldPix21 <= '0', '1' after 112 ns, '0' after 122 ns, '1' after 152 ns, '0' after 162 ns, '1' after 192 ns, '0' after 202 ns, '1' after 232 ns, '0' after 242 ns;
-
- S_ldPix31 <= '0', '1' after 122 ns, '0' after 132 ns, '1' after 162 ns, '0' after 172 ns, '1' after 202 ns, '0' after 212 ns, '1' after 242 ns, '0' after 252 ns;
-
- S_shReg <= '0', '1' after 132 ns, '0' after 142 ns, '1' after 172 ns, '0' after 182 ns, '1' after 212 ns, '0' after 222 ns, '1' after 252 ns, '0' after 262 ns;
-
+ S_ldPix11 <= '0', '1' after 102 ns, '0' after 112 ns, '1' after 142 ns, '0' after 152 ns, '1' after 182 ns, '0' after 192 ns, '1' after 222 ns, '0' after 232 ns;
+ S_ldPix21 <= '0', '1' after 112 ns, '0' after 122 ns, '1' after 152 ns, '0' after 162 ns, '1' after 192 ns, '0' after 202 ns, '1' after 232 ns, '0' after 242 ns;
+ S_ldPix31 <= '0', '1' after 122 ns, '0' after 132 ns, '1' after 162 ns, '0' after 172 ns, '1' after 202 ns, '0' after 212 ns, '1' after 242 ns, '0' after 252 ns;
+ S_shReg <= '0', '1' after 132 ns, '0' after 142 ns, '1' after 172 ns, '0' after 182 ns, '1' after 212 ns, '0' after 222 ns, '1' after 252 ns, '0' after 262 ns;
- process (S_clk, s_reset)
- begin
- if s_reset = '1' then
- S_pixel <= (others => '0');
- elsif (rising_edge(S_clk)) then
- S_pixel <= STD_LOGIC_VECTOR(unsigned(S_pixel) + 1);
- end if;
- end process;
-
+ process (S_clk)
+ begin
+ if (rising_edge(S_clk)) then
+ S_pixel <= std_logic_vector(unsigned(S_pixel) + 1);
+ end if;
+ end process;
- regUnit_1 : entity work.regUnit
- port map (
- clk => S_clk,
- reset => S_reset,
- I_pixel => S_pixel,
- I_ldPix11 => S_ldPix11,
- I_ldPix21 => S_ldPix21,
- I_ldPix31 => S_ldPix31,
- I_shReg => S_shReg,
- O_Pix11 => S_Pix11,
- O_Pix12 => S_Pix12,
- O_Pix13 => S_Pix13,
- O_Pix21 => S_Pix21,
- O_Pix22 => S_Pix22,
- O_Pix23 => S_Pix23,
- O_Pix31 => S_Pix31,
- O_Pix32 => S_Pix32,
- O_Pix33 => S_Pix33);
+ regUnit_1 : entity work.regUnit
+ port map (
+ I_clk => S_clk,
+ I_pixel => S_pixel,
+ I_ldPix11 => S_ldPix11,
+ I_ldPix21 => S_ldPix21,
+ I_ldPix31 => S_ldPix31,
+ I_shReg => S_shReg,
+ O_Pix11 => S_Pix11,
+ O_Pix12 => S_Pix12,
+ O_Pix13 => S_Pix13,
+ O_Pix21 => S_Pix21,
+ O_Pix22 => S_Pix22,
+ O_Pix23 => S_Pix23,
+ O_Pix31 => S_Pix31,
+ O_Pix32 => S_Pix32,
+ O_Pix33 => S_Pix33);
end architecture archi_tb_regUnit;
diff --git a/src/tb_sobelProc.vhd b/src/tb_sobelProc.vhd
index a5cc580..e0ca655 100644
--- a/src/tb_sobelProc.vhd
+++ b/src/tb_sobelProc.vhd
@@ -7,56 +7,55 @@ entity tb_sobelProc is
end entity tb_sobelProc;
architecture archi_tb_sobelProc of tb_sobelProc is
- component sobelProc is
- Port ( clk,reset : in STD_LOGIC;
- I_go : in STD_LOGIC;
- -- interface avec la mémoire IN (lecture)
- O_enM_R : out STD_LOGIC;
- O_ADR_R : out STD_LOGIC_VECTOR (13 downto 0);
- I_pixel : in STD_LOGIC_VECTOR (7 downto 0); -- Pixel from memory IN
- -- interface avec la mémoire OUT (écriture)
- O_enM_W : out STD_LOGIC;
- O_ADR_W : out STD_LOGIC_VECTOR (13 downto 0);
- O_pixEdge : out STD_LOGIC; -- Edge to memory OUT
- -- signal de commande vers le contrôleur VGA
- O_StartDisplay : out STD_LOGIC
- );
- end component sobelProc;
-
-signal S_clk : STD_LOGIC := '0';
-signal S_reset : STD_LOGIC;
-signal S_go : STD_LOGIC;
-signal S_enM_R : STD_LOGIC;
-signal S_ADR_R : STD_LOGIC_VECTOR (13 downto 0);
-signal S_pixel : STD_LOGIC_VECTOR (7 downto 0);
-signal S_enM_W : STD_LOGIC;
-signal S_ADR_W : STD_LOGIC_VECTOR (13 downto 0);
-signal S_pixEdge : STD_LOGIC;
-signal S_StartDisplay : STD_LOGIC;
-
+ component sobelProc is
+ port (I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_go : in std_logic;
+ -- interface avec la mémoire IN (lecture)
+ O_enM_R : out std_logic;
+ O_ADR_R : out std_logic_vector (13 downto 0);
+ I_pixel : in std_logic_vector (7 downto 0); -- Pixel from memory IN
+ -- interface avec la mémoire OUT (écriture)
+ O_enM_W : out std_logic;
+ O_ADR_W : out std_logic_vector (13 downto 0);
+ O_pixEdge : out std_logic; -- Edge to memory OUT
+ -- signal de commande vers le contrôleur VGA
+ O_StartDisplay : out std_logic
+ );
+ end component sobelProc;
+
+ signal S_clk : std_logic := '0';
+ signal S_I_rst : std_logic;
+ signal S_go : std_logic;
+ signal S_enM_R : std_logic;
+ signal S_ADR_R : std_logic_vector (13 downto 0);
+ signal S_pixel : std_logic_vector (7 downto 0);
+ signal S_enM_W : std_logic;
+ signal S_ADR_W : std_logic_vector (13 downto 0);
+ signal S_pixEdge : std_logic;
+ signal S_StartDisplay : std_logic;
begin
- S_pixel <= "00000111";
-
- S_clk <= not S_clk after 5 ns;
- S_reset <= '1', '0' after 64 ns;
- S_go <= '0', '1' after 164 ns, '0' after 264 ns;
-
- sobelProc_1 : entity work.sobelProc
- port map (
- clk => S_clk ,
- reset => S_reset ,
- I_go => S_go ,
- O_enM_R => S_enM_R ,
- O_ADR_R => S_ADR_R ,
- I_pixel => S_pixel ,
- O_enM_W => S_enM_W ,
- O_ADR_W => S_ADR_W ,
- O_pixEdge => S_pixEdge ,
- O_StartDisplay => S_StartDisplay
- );
-
+ S_pixel <= "00000111";
+
+ S_clk <= not S_clk after 5 ns;
+ S_I_rst <= '1', '0' after 64 ns;
+ S_go <= '0', '1' after 164 ns, '0' after 264 ns;
+
+ sobelProc_1 : entity work.sobelProc
+ port map (
+ I_clk => S_clk,
+ I_rst => S_I_rst,
+ I_go => S_go,
+ O_enM_R => S_enM_R,
+ O_ADR_R => S_ADR_R,
+ I_pixel => S_pixel,
+ O_enM_W => S_enM_W,
+ O_ADR_W => S_ADR_W,
+ O_pixEdge => S_pixEdge,
+ O_StartDisplay => S_StartDisplay
+ );
end architecture archi_tb_sobelProc;
diff --git a/src/tb_sobelSys.vhd b/src/tb_sobelSys.vhd
index c578049..7f243f4 100644
--- a/src/tb_sobelSys.vhd
+++ b/src/tb_sobelSys.vhd
@@ -7,49 +7,45 @@ entity tb_sobelSys is
end entity tb_sobelSys;
architecture archi_tb_sobelSys of tb_sobelSys is
- component sobelSys is
- Port ( clk_i : in STD_LOGIC;
- reset_i : in STD_LOGIC;
- go_i : in STD_LOGIC;
- -- VGA Output Signals
- vga_hs_o : out STD_LOGIC; -- HSYNC OUT
- vga_vs_o : out STD_LOGIC; -- VSYNC OUT
- vga_red_o : out STD_LOGIC_VECTOR (3 downto 0); -- Red signal going to the VGA interface
- vga_green_o : out STD_LOGIC_VECTOR (3 downto 0); -- Green signal going to the VGA interface
- vga_blue_o : out STD_LOGIC_VECTOR (3 downto 0) -- Blue signal going to the VGA interface
- );
- end component sobelSys;
-
-
-
- signal S_clk_i : std_logic := '0';
- signal S_reset_i : std_logic;
- signal S_go_i : std_logic;
- signal S_vga_hs_o : std_logic;
- signal S_vga_vs_o : std_logic;
- signal S_vga_red_o : STD_LOGIC_VECTOR (3 downto 0);
- signal S_vga_green_o : STD_LOGIC_VECTOR (3 downto 0);
- signal S_vga_blue_o : STD_LOGIC_VECTOR (3 downto 0);
-
-begin
+ component sobelSys is
+ port (I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_go : in std_logic;
+ -- VGA Output Signals
+ O_vga_hs : out std_logic; -- HSYNC OUT
+ O_vga_vs : out std_logic; -- VSYNC OUT
+ O_vga_red : out std_logic_vector (3 downto 0); -- Red signal going to the VGA interface
+ O_vga_green : out std_logic_vector (3 downto 0); -- Green signal going to the VGA interface
+ O_vga_blue : out std_logic_vector (3 downto 0) -- Blue signal going to the VGA interface
+ );
+ end component sobelSys;
+
+ signal S_I_clk : std_logic := '0';
+ signal S_I_rst : std_logic;
+ signal S_go_i : std_logic;
+ signal S_vga_hs_o : std_logic;
+ signal S_vga_vs_o : std_logic;
+ signal S_vga_red_o : std_logic_vector (3 downto 0);
+ signal S_vga_green_o : std_logic_vector (3 downto 0);
+ signal S_vga_blue_o : std_logic_vector (3 downto 0);
- S_clk_i <= not S_clk_i after 5 ns;
- S_reset_i <= '1', '0' after 2064 ns;
- S_go_i <= '0', '1' after 2264 ns, '0' after 2664 ns;
-
-
- sobelSys_1 : entity work.sobelSys
- port map (
- clk_i => S_clk_i ,
- reset_i => S_reset_i ,
- go_i => S_go_i ,
- vga_hs_o => S_vga_hs_o ,
- vga_vs_o => S_vga_vs_o ,
- vga_red_o => S_vga_red_o ,
- vga_green_o => S_vga_green_o ,
- vga_blue_o => S_vga_blue_o
- );
+begin
+ S_I_clk <= not S_I_clk after 5 ns;
+ S_I_rst <= '1', '0' after 2064 ns;
+ S_go_i <= '0', '1' after 2264 ns, '0' after 2664 ns;
+
+ sobelSys_1 : entity work.sobelSys
+ port map (
+ I_clk => S_I_clk,
+ I_rst => S_I_rst,
+ I_go => S_go_i,
+ O_vga_hs => S_vga_hs_o,
+ O_vga_vs => S_vga_vs_o,
+ O_vga_red => S_vga_red_o,
+ O_vga_green => S_vga_green_o,
+ O_vga_blue => S_vga_blue_o
+ );
end architecture archi_tb_sobelSys;
diff --git a/src/vga_nexys4_2regions.vhd b/src/vga_nexys4_2regions.vhd
index 8c1a260..8e9d3d6 100644
--- a/src/vga_nexys4_2regions.vhd
+++ b/src/vga_nexys4_2regions.vhd
@@ -3,58 +3,58 @@
-- Author: Albert Fazakas adapted from Alec Wyen and Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
---
--- Create Date: 13:01:51 02/15/2013
--- Design Name:
--- Module Name: Vga - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
+--
+-- Create Date: 13:01:51 02/15/2013
+-- Design Name:
+-- Module Name: Vga - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
-- This module represents the Vga controller that creates the HSYNC and VSYNC signals
-- for the VGA screen and formats the 4-bit R, G and B signals to display various items
-- on the screen:
-- - A moving colorbar in the background
--- - A Digilent - Analog Devices logo for the Nexys4 board, the RGB data is provided
+-- - A Digilent - Analog Devices logo for the Nexys4 board, the RGB data is provided
-- by the LogoDisplay component. The logo bitmap is stored in the BRAM_1 Block RAM in .ngc format.
-- - The FPGA temperature on a 0..80C scale. Temperature data is taken from the XADC
-- component in the Artix-7 FPGA, provided by the upper level FPGAMonitor component and the RGB data is
-- provided by the Inst_XadcTempDisplay instance of the TempDisplay component.
--- - The Nexys4 Onboard ADT7420 Temperature Sensor temperature on a 0..80C scale.
+-- - The Nexys4 Onboard ADT7420 Temperature Sensor temperature on a 0..80C scale.
-- Temperature data is provided by the upper level TempSensorCtl component and the RGB data is
-- provided by the Inst_Adt7420TempDisplay instance of the TempDisplay component.
--- - The Nexys4 Onboard ADXL362 Accelerometer Temperature Sensor temperature on a 0..80C scale.
+-- - The Nexys4 Onboard ADXL362 Accelerometer Temperature Sensor temperature on a 0..80C scale.
-- Temperature data is provided by the upper level AccelerometerCtl component and the RGB data is
-- provided by the Inst_Adxl362TempDisplay instance of the TempDisplay component.
--- - The R, G and B data which is also sent to the Nexys4 onboard RGB Leds LD16 and LD17. The
+-- - The R, G and B data which is also sent to the Nexys4 onboard RGB Leds LD16 and LD17. The
-- incomming RGB Led data is taken from the upper level RgbLed component and the formatted RGB data is provided
-- by the RGBLedDisplay component.
-- - The audio signal coming from the Nexys4 Onboard ADMP421 Omnidirectional Microphone. The formatted
-- RGB data is provided by the MicDisplay component.
--- - The X and Y acceleration in a form of a moving box and the acceleration magnitude determined by
--- the SQRT (X^2 + Y^2 + Z^2) formula. The acceleration and magnitude data is provided by the upper level
+-- - The X and Y acceleration in a form of a moving box and the acceleration magnitude determined by
+-- the SQRT (X^2 + Y^2 + Z^2) formula. The acceleration and magnitude data is provided by the upper level
-- AccelerometerCtl component and the formatted RGB data is provided by the AccelDisplay component.
--- - The mouse cursor on the top on all of the items. The USB mouse should be connected to the Nexys4 board before
--- the FPGA is configured. The mouse cursor data is provided by the upper level MouseCtl component and the
+-- - The mouse cursor on the top on all of the items. The USB mouse should be connected to the Nexys4 board before
+-- the FPGA is configured. The mouse cursor data is provided by the upper level MouseCtl component and the
-- formatted RGB data for the mouse cursor shape is provided by the MouseDisplay component.
-- - An overlay that displayed the frames and text for the displayed items described above. The overlay data is
-- stored in the overlay_bram Block RAM in the .ngc format and the data is provided by the OverlayCtl component.
-- The Vga controller holds the synchronization signal generation, the moving colorbar generation and the main
-- multiplexers for the outgoing R, G and B signals. Also the 108 MHz pixel clock (pxl_clk) generator is instantiated
-- inside the Vga controller.
--- The current resolution is 1280X1024 pixels, however, other resolutions can also be selected by
+-- The current resolution is 1280X1024 pixels, however, other resolutions can also be selected by
-- commenting/uncommenting the corresponding VGA resolution constants. In the case when a different resolution
-- is selected, the pixel clock generator output frequency also has to be updated accordingly.
--
--- Revision:
+-- Revision:
-- Revision 0.01 - File Created
--- Additional Comments:
+-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
@@ -67,27 +67,27 @@ use ieee.math_real.all;
--use UNISIM.VComponents.all;
entity vga_nexys4_2regions is
- Port ( clk_i : in STD_LOGIC;
- reset_i : in STD_LOGIC;
- -- VGA Output Signals
- vga_hs_o : out STD_LOGIC; -- HSYNC OUT
- vga_vs_o : out STD_LOGIC; -- VSYNC OUT
- vga_red_o : out STD_LOGIC_VECTOR (3 downto 0); -- Red signal going to the VGA interface
- vga_green_o : out STD_LOGIC_VECTOR (3 downto 0); -- Green signal going to the VGA interface
- vga_blue_o : out STD_LOGIC_VECTOR (3 downto 0); -- Blue signal going to the VGA interface
- ----------------------
- -- I/O internes, pour lire la mémoire de sortie de Sobel
- O_clk_25MHz : out STD_LOGIC;
- I_StartDisplay : in STD_LOGIC;
- ----
- O_enM_vga_region1 : out STD_LOGIC;
- O_addr_M_vga_region1 : out STD_LOGIC_VECTOR(13 downto 0);
- I_data_M_vga_region1 : in STD_LOGIC_VECTOR(7 downto 0);
- -----
- O_enM_vga_region2 : out STD_LOGIC;
- O_addr_M_vga_region2 : out STD_LOGIC_VECTOR(13 downto 0);
- I_data_M_vga_region2 : in STD_LOGIC_VECTOR(7 downto 0)
- );
+ port (clk_i : in std_logic;
+ reset_i : in std_logic;
+ -- VGA Output Signals
+ vga_hs_o : out std_logic; -- HSYNC OUT
+ vga_vs_o : out std_logic; -- VSYNC OUT
+ vga_red_o : out std_logic_vector (3 downto 0); -- Red signal going to the VGA interface
+ vga_green_o : out std_logic_vector (3 downto 0); -- Green signal going to the VGA interface
+ vga_blue_o : out std_logic_vector (3 downto 0); -- Blue signal going to the VGA interface
+ ----------------------
+ -- I/O internes, pour lire la mémoire de sortie de Sobel
+ O_clk_25MHz : out std_logic;
+ I_StartDisplay : in std_logic;
+ ----
+ O_enM_vga_region1 : out std_logic;
+ O_addr_M_vga_region1 : out std_logic_vector(13 downto 0);
+ I_data_M_vga_region1 : in std_logic_vector(7 downto 0);
+ -----
+ O_enM_vga_region2 : out std_logic;
+ O_addr_M_vga_region2 : out std_logic_vector(13 downto 0);
+ I_data_M_vga_region2 : in std_logic_vector(7 downto 0)
+ );
end vga_nexys4_2regions;
architecture Behavioral of vga_nexys4_2regions is
@@ -98,20 +98,20 @@ architecture Behavioral of vga_nexys4_2regions is
-------------------------------------------------------------------------
- -- 108 MHz Pixel Clock needed for a resolution of 1280*1024 pixels
- -- 25 MHz Pixel Clock needed for a resolution of 640*480 pixels
+ -- 108 MHz Pixel Clock needed for a resolution of 1280*1024 pixels
+ -- 25 MHz Pixel Clock needed for a resolution of 640*480 pixels
- -- To generate the 25 MHz Pixel Clock
- COMPONENT clk_wiz_vga_25MHz
- PORT
- (-- Clock in ports
- CLK_IN1 : in std_logic;
- -- Clock out ports
- CLK_OUT1 : out std_logic;
- -- Status and control signals
- LOCKED : out std_logic
- );
- END COMPONENT;
+ -- To generate the 25 MHz Pixel Clock
+ component clk_wiz_vga_25MHz
+ port
+ ( -- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Clock out ports
+ CLK_OUT1 : out std_logic;
+ -- Status and control signals
+ LOCKED : out std_logic
+ );
+ end component;
@@ -122,20 +122,20 @@ architecture Behavioral of vga_nexys4_2regions is
-------------------------------------------------------------
---***640x480@60Hz***--
-constant FRAME_WIDTH : natural := 640;
-constant FRAME_HEIGHT : natural := 480;
+--***640x480@60Hz***--
+ constant FRAME_WIDTH : natural := 640;
+ constant FRAME_HEIGHT : natural := 480;
-constant H_FP : natural := 16; --H front porch width (pixels)
-constant H_PW : natural := 96; --H sync pulse width (pixels)
-constant H_MAX : natural := 800; --H total period (pixels)
+ constant H_FP : natural := 16; --H front porch width (pixels)
+ constant H_PW : natural := 96; --H sync pulse width (pixels)
+ constant H_MAX : natural := 800; --H total period (pixels)
-constant V_FP : natural := 10; --V front porch width (lines)
-constant V_PW : natural := 2; --V sync pulse width (lines)
-constant V_MAX : natural := 525; --V total period (lines)
+ constant V_FP : natural := 10; --V front porch width (lines)
+ constant V_PW : natural := 2; --V sync pulse width (lines)
+ constant V_MAX : natural := 525; --V total period (lines)
-constant H_POL : std_logic := '0';
-constant V_POL : std_logic := '0';
+ constant H_POL : std_logic := '0';
+ constant V_POL : std_logic := '0';
--***800x600@60Hz***--
--constant FRAME_WIDTH : natural := 800;
@@ -187,32 +187,32 @@ constant V_POL : std_logic := '0';
-- Constants for setting the displayed logo size and coordinates
------------------------------------------------------------------
--- constant SZ_LOGO_WIDTH : natural := 335; -- Width of the logo frame
--- constant SZ_LOGO_HEIGHT : natural := 280; -- Height of the logo frame
+-- constant SZ_LOGO_WIDTH : natural := 335; -- Width of the logo frame
+-- constant SZ_LOGO_HEIGHT : natural := 280; -- Height of the logo frame
--- constant FRM_LOGO_H_LOC : natural := 25; -- Starting horizontal location of the logo frame
--- constant FRM_LOGO_V_LOC : natural := 176; -- Starting vertical location of the logo frame
+-- constant FRM_LOGO_H_LOC : natural := 25; -- Starting horizontal location of the logo frame
+-- constant FRM_LOGO_V_LOC : natural := 176; -- Starting vertical location of the logo frame
-- Logo frame limits
--- constant LOGO_LEFT : natural := FRM_LOGO_H_LOC - 1;
--- constant LOGO_RIGHT : natural := FRM_LOGO_H_LOC + SZ_LOGO_WIDTH + 1;
--- constant LOGO_TOP : natural := FRM_LOGO_V_LOC - 1;
--- constant LOGO_BOTTOM : natural := FRM_LOGO_V_LOC + SZ_LOGO_HEIGHT + 1;
+-- constant LOGO_LEFT : natural := FRM_LOGO_H_LOC - 1;
+-- constant LOGO_RIGHT : natural := FRM_LOGO_H_LOC + SZ_LOGO_WIDTH + 1;
+-- constant LOGO_TOP : natural := FRM_LOGO_V_LOC - 1;
+-- constant LOGO_BOTTOM : natural := FRM_LOGO_V_LOC + SZ_LOGO_HEIGHT + 1;
-- Constants for setting size and location for the Accelerometer display
--------------------------------------------------------------------------
-- Original Image frame limits
-constant REGION1_LEFT : natural := 200;
-constant REGION1_RIGHT : natural := REGION1_LEFT + 101;
-constant REGION1_TOP : natural := 190;
-constant REGION1_BOTTOM : natural := REGION1_TOP + 101;
+ constant REGION1_LEFT : natural := 200;
+ constant REGION1_RIGHT : natural := REGION1_LEFT + 101;
+ constant REGION1_TOP : natural := 190;
+ constant REGION1_BOTTOM : natural := REGION1_TOP + 101;
-- Edge Image frame limits
-constant REGION2_LEFT : natural := 340;
-constant REGION2_RIGHT : natural := REGION2_LEFT + 101;
-constant REGION2_TOP : natural := 190;
-constant REGION2_BOTTOM : natural := REGION2_TOP + 101;
+ constant REGION2_LEFT : natural := 340;
+ constant REGION2_RIGHT : natural := REGION2_LEFT + 101;
+ constant REGION2_TOP : natural := 190;
+ constant REGION2_BOTTOM : natural := REGION2_TOP + 101;
@@ -229,33 +229,33 @@ constant REGION2_BOTTOM : natural := REGION2_TOP + 101;
-------------------------------------------------------------------------
-- Pixel clock, in this case 25 MHz
-signal pxl_clk : std_logic;
+ signal pxl_clk : std_logic;
-- The active signal is used to signal the active region of the screen (when not blank)
-signal active : std_logic;
+ signal active : std_logic;
-- Horizontal and Vertical counters
-signal h_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0');
-signal v_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0');
+ signal h_cntr_reg : std_logic_vector(11 downto 0) := (others => '0');
+ signal v_cntr_reg : std_logic_vector(11 downto 0) := (others => '0');
-- Horizontal and Vertical Sync
-signal h_sync_reg : std_logic := not(H_POL);
-signal v_sync_reg : std_logic := not(V_POL);
+ signal h_sync_reg : std_logic := not(H_POL);
+ signal v_sync_reg : std_logic := not(V_POL);
-- Pipe Horizontal and Vertical Sync
-signal h_sync_reg_dly : std_logic := not(H_POL);
-signal v_sync_reg_dly : std_logic := not(V_POL);
+ signal h_sync_reg_dly : std_logic := not(H_POL);
+ signal v_sync_reg_dly : std_logic := not(V_POL);
-- VGA R, G and B signals coming from the main multiplexers
-signal vga_red_cmb : std_logic_vector(3 downto 0);
-signal vga_green_cmb : std_logic_vector(3 downto 0);
-signal vga_blue_cmb : std_logic_vector(3 downto 0);
+ signal vga_red_cmb : std_logic_vector(3 downto 0);
+ signal vga_green_cmb : std_logic_vector(3 downto 0);
+ signal vga_blue_cmb : std_logic_vector(3 downto 0);
--The main VGA R, G and B signals, validated by active
-signal vga_red : std_logic_vector(3 downto 0);
-signal vga_green : std_logic_vector(3 downto 0);
-signal vga_blue : std_logic_vector(3 downto 0);
+ signal vga_red : std_logic_vector(3 downto 0);
+ signal vga_green : std_logic_vector(3 downto 0);
+ signal vga_blue : std_logic_vector(3 downto 0);
-- Register VGA R, G and B signals
-signal vga_red_reg : std_logic_vector(3 downto 0) := (others =>'0');
-signal vga_green_reg : std_logic_vector(3 downto 0) := (others =>'0');
-signal vga_blue_reg : std_logic_vector(3 downto 0) := (others =>'0');
+ signal vga_red_reg : std_logic_vector(3 downto 0) := (others => '0');
+ signal vga_green_reg : std_logic_vector(3 downto 0) := (others => '0');
+ signal vga_blue_reg : std_logic_vector(3 downto 0) := (others => '0');
-------------------------------------------------------------------------
@@ -267,222 +267,222 @@ signal vga_blue_reg : std_logic_vector(3 downto 0) := (others =>'0');
-- Signals for generating the background (moving colorbar)
-----------------------------------------------------------
-- Colorbar red, greeen and blue signals
-signal bg_red : std_logic_vector(3 downto 0);
-signal bg_blue : std_logic_vector(3 downto 0);
-signal bg_green : std_logic_vector(3 downto 0);
+ signal bg_red : std_logic_vector(3 downto 0);
+ signal bg_blue : std_logic_vector(3 downto 0);
+ signal bg_green : std_logic_vector(3 downto 0);
-- Added
-signal S_inc_adr_region1 : std_logic;
-signal S_inc_adr_region2 : std_logic;
-signal S_adr_region1 : integer range 0 to 9999;
-signal S_adr_region2 : integer range 0 to 9999;
+ signal S_inc_adr_region1 : std_logic;
+ signal S_inc_adr_region2 : std_logic;
+ signal S_adr_region1 : integer range 0 to 9999;
+ signal S_adr_region2 : integer range 0 to 9999;
begin
-
+
------------------------------------
--- Generate the 25 MHz pixel clock
+-- Generate the 25 MHz pixel clock
------------------------------------
- Inst_clk_wiz_vga_25MHz : clk_wiz_vga_25MHz
- port map
- (-- Clock in ports
- CLK_IN1 => CLK_I,
- -- Clock out ports
- CLK_OUT1 => pxl_clk,
- -- Status and control signals
- LOCKED => open
- );
-
- O_clk_25MHz <= pxl_clk;
+ Inst_clk_wiz_vga_25MHz : clk_wiz_vga_25MHz
+ port map
+ ( -- Clock in ports
+ CLK_IN1 => CLK_I,
+ -- Clock out ports
+ CLK_OUT1 => pxl_clk,
+ -- Status and control signals
+ LOCKED => open
+ );
+
+ O_clk_25MHz <= pxl_clk;
---------------------------------------------------------------
-- Generate Horizontal, Vertical counters and the Sync signals
---------------------------------------------------------------
- -- Horizontal counter
- process (pxl_clk)
- begin
- if (rising_edge(pxl_clk)) then
- if (h_cntr_reg = (H_MAX - 1)) then
- h_cntr_reg <= (others =>'0');
- else
- h_cntr_reg <= h_cntr_reg + 1;
- end if;
- end if;
- end process;
- -- Vertical counter
- process (pxl_clk)
- begin
- if (rising_edge(pxl_clk)) then
- if ((h_cntr_reg = (H_MAX - 1)) and (v_cntr_reg = (V_MAX - 1))) then
- v_cntr_reg <= (others =>'0');
- elsif (h_cntr_reg = (H_MAX - 1)) then
- v_cntr_reg <= v_cntr_reg + 1;
- end if;
- end if;
- end process;
- -- Horizontal sync
- process (pxl_clk)
- begin
- if (rising_edge(pxl_clk)) then
- if (h_cntr_reg >= (H_FP + FRAME_WIDTH - 1)) and (h_cntr_reg < (H_FP + FRAME_WIDTH + H_PW - 1)) then
- h_sync_reg <= H_POL;
- else
- h_sync_reg <= not(H_POL);
- end if;
- end if;
- end process;
- -- Vertical sync
- process (pxl_clk)
- begin
- if (rising_edge(pxl_clk)) then
- if (v_cntr_reg >= (V_FP + FRAME_HEIGHT - 1)) and (v_cntr_reg < (V_FP + FRAME_HEIGHT + V_PW - 1)) then
- v_sync_reg <= V_POL;
- else
- v_sync_reg <= not(V_POL);
- end if;
- end if;
- end process;
-
+ -- Horizontal counter
+ process (pxl_clk)
+ begin
+ if (rising_edge(pxl_clk)) then
+ if (h_cntr_reg = (H_MAX - 1)) then
+ h_cntr_reg <= (others => '0');
+ else
+ h_cntr_reg <= h_cntr_reg + 1;
+ end if;
+ end if;
+ end process;
+ -- Vertical counter
+ process (pxl_clk)
+ begin
+ if (rising_edge(pxl_clk)) then
+ if ((h_cntr_reg = (H_MAX - 1)) and (v_cntr_reg = (V_MAX - 1))) then
+ v_cntr_reg <= (others => '0');
+ elsif (h_cntr_reg = (H_MAX - 1)) then
+ v_cntr_reg <= v_cntr_reg + 1;
+ end if;
+ end if;
+ end process;
+ -- Horizontal sync
+ process (pxl_clk)
+ begin
+ if (rising_edge(pxl_clk)) then
+ if (h_cntr_reg >= (H_FP + FRAME_WIDTH - 1)) and (h_cntr_reg < (H_FP + FRAME_WIDTH + H_PW - 1)) then
+ h_sync_reg <= H_POL;
+ else
+ h_sync_reg <= not(H_POL);
+ end if;
+ end if;
+ end process;
+ -- Vertical sync
+ process (pxl_clk)
+ begin
+ if (rising_edge(pxl_clk)) then
+ if (v_cntr_reg >= (V_FP + FRAME_HEIGHT - 1)) and (v_cntr_reg < (V_FP + FRAME_HEIGHT + V_PW - 1)) then
+ v_sync_reg <= V_POL;
+ else
+ v_sync_reg <= not(V_POL);
+ end if;
+ end if;
+ end process;
+
+--------------------
+-- The active
--------------------
--- The active
---------------------
- -- active signal
- active <= '1' when h_cntr_reg < FRAME_WIDTH and v_cntr_reg < FRAME_HEIGHT else '0';
+ -- active signal
+ active <= '1' when h_cntr_reg < FRAME_WIDTH and v_cntr_reg < FRAME_HEIGHT else '0';
---------------------------------------
-- Generate colorbar background
---------------------------------------
-
- bg_red <= h_cntr_reg(3 downto 0) when (h_cntr_reg < 100)
- else h_cntr_reg(7 downto 4) when (h_cntr_reg < 400)
- else "0101";
- bg_green <= "0011" when (h_cntr_reg < 100)
- else "1001" when (h_cntr_reg < 400)
- else "0101";
+ bg_red <= h_cntr_reg(3 downto 0) when (h_cntr_reg < 100)
+ else h_cntr_reg(7 downto 4) when (h_cntr_reg < 400)
+ else "0101";
+
+ bg_green <= "0011" when (h_cntr_reg < 100)
+ else "1001" when (h_cntr_reg < 400)
+ else "0101";
+
+ bg_blue <= v_cntr_reg(3 downto 0) when (v_cntr_reg < 100)
+ else v_cntr_reg(7 downto 4) when (v_cntr_reg < 400)
+ else "0100";
- bg_blue <= v_cntr_reg(3 downto 0) when (v_cntr_reg < 100)
- else v_cntr_reg(7 downto 4) when (v_cntr_reg < 400)
- else "0100";
-
---------------------------------------
-- Generate addresses to the memory frame buffer Region1
---------------------------------------
- process(reset_i,pxl_clk)
- begin
- if (reset_i = '1') then
- S_adr_region1 <= 9999;
- elsif(rising_edge(pxl_clk)) then
- if I_StartDisplay = '1' then
- if S_inc_adr_region1 = '1' then
- if S_adr_region1 = 0 then
- S_adr_region1 <= 9999;
- else
- S_adr_region1 <= S_adr_region1 - 1;
- end if;
- end if;
- end if;
- end if;
- end process;
-
- O_addr_M_vga_region1 <= conv_std_logic_vector(S_adr_region1, 14);
-
- S_inc_adr_region1 <= '1' when (h_cntr_reg = REGION1_LEFT and v_cntr_reg = (REGION1_TOP+1)) OR
- (h_cntr_reg > REGION1_LEFT and h_cntr_reg < REGION1_RIGHT
- and v_cntr_reg > REGION1_TOP and v_cntr_reg < (REGION1_BOTTOM-1)) OR
- (h_cntr_reg > REGION1_LEFT and h_cntr_reg < (REGION1_RIGHT-1) and v_cntr_reg = (REGION1_BOTTOM-1))
- else '0';
-
- O_enM_vga_region1 <= S_inc_adr_region1;
+ process(reset_i, pxl_clk)
+ begin
+ if (reset_i = '1') then
+ S_adr_region1 <= 9999;
+ elsif(rising_edge(pxl_clk)) then
+ if I_StartDisplay = '1' then
+ if S_inc_adr_region1 = '1' then
+ if S_adr_region1 = 0 then
+ S_adr_region1 <= 9999;
+ else
+ S_adr_region1 <= S_adr_region1 - 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ O_addr_M_vga_region1 <= conv_std_logic_vector(S_adr_region1, 14);
+
+ S_inc_adr_region1 <= '1' when (h_cntr_reg = REGION1_LEFT and v_cntr_reg = (REGION1_TOP+1)) or
+ (h_cntr_reg > REGION1_LEFT and h_cntr_reg < REGION1_RIGHT
+ and v_cntr_reg > REGION1_TOP and v_cntr_reg < (REGION1_BOTTOM-1)) or
+ (h_cntr_reg > REGION1_LEFT and h_cntr_reg < (REGION1_RIGHT-1) and v_cntr_reg = (REGION1_BOTTOM-1))
+ else '0';
+
+ O_enM_vga_region1 <= S_inc_adr_region1;
---------------------------------------
-- Generate addresses to the memory frame buffer Region2
---------------------------------------
- process(reset_i,pxl_clk)
- begin
- if (reset_i = '1') then
- S_adr_region2 <= 9999;
- elsif(rising_edge(pxl_clk)) then
- if I_StartDisplay = '1' then
- if S_inc_adr_region2 = '1' then
- if S_adr_region2 = 0 then
- S_adr_region2 <= 9999;
- else
- S_adr_region2 <= S_adr_region2 - 1;
- end if;
- end if;
- end if;
- end if;
- end process;
-
- O_addr_M_vga_region2 <= conv_std_logic_vector(S_adr_region2, 14);
-
- S_inc_adr_region2 <= '1' when (h_cntr_reg = REGION2_LEFT and v_cntr_reg = (REGION2_TOP + 1)) OR
- (h_cntr_reg > REGION2_LEFT and h_cntr_reg < REGION2_RIGHT
- and v_cntr_reg > REGION2_TOP and v_cntr_reg < (REGION2_BOTTOM-1)) OR
- (h_cntr_reg > REGION2_LEFT and h_cntr_reg < (REGION2_RIGHT-1) and v_cntr_reg = (REGION2_BOTTOM-1))
- else '0';
-
- O_enM_vga_region2 <= S_inc_adr_region2;
-
+ process(reset_i, pxl_clk)
+ begin
+ if (reset_i = '1') then
+ S_adr_region2 <= 9999;
+ elsif(rising_edge(pxl_clk)) then
+ if I_StartDisplay = '1' then
+ if S_inc_adr_region2 = '1' then
+ if S_adr_region2 = 0 then
+ S_adr_region2 <= 9999;
+ else
+ S_adr_region2 <= S_adr_region2 - 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ O_addr_M_vga_region2 <= conv_std_logic_vector(S_adr_region2, 14);
+
+ S_inc_adr_region2 <= '1' when (h_cntr_reg = REGION2_LEFT and v_cntr_reg = (REGION2_TOP + 1)) or
+ (h_cntr_reg > REGION2_LEFT and h_cntr_reg < REGION2_RIGHT
+ and v_cntr_reg > REGION2_TOP and v_cntr_reg < (REGION2_BOTTOM-1)) or
+ (h_cntr_reg > REGION2_LEFT and h_cntr_reg < (REGION2_RIGHT-1) and v_cntr_reg = (REGION2_BOTTOM-1))
+ else '0';
+
+ O_enM_vga_region2 <= S_inc_adr_region2;
+
-------------------------------------------------------------
-- Main Multiplexers for the VGA Red, Green and Blue signals
-
- vga_red <= I_data_M_vga_region1(7 downto 4) when h_cntr_reg > REGION1_LEFT+2 and h_cntr_reg < REGION1_RIGHT-2
- and v_cntr_reg > REGION1_TOP+2 and v_cntr_reg < REGION1_BOTTOM-2
- else I_data_M_vga_region2(7 downto 4) when h_cntr_reg > REGION2_LEFT+2 and h_cntr_reg < REGION2_RIGHT-2
- and v_cntr_reg > REGION2_TOP+2 and v_cntr_reg < REGION2_BOTTOM-2
- else bg_red;
-
- vga_green <= I_data_M_vga_region1(7 downto 4) when h_cntr_reg > REGION1_LEFT+2 and h_cntr_reg < REGION1_RIGHT-2
- and v_cntr_reg > REGION1_TOP+2 and v_cntr_reg < REGION1_BOTTOM-2
- else I_data_M_vga_region2(7 downto 4) when h_cntr_reg > REGION2_LEFT+2 and h_cntr_reg < REGION2_RIGHT-2
- and v_cntr_reg > REGION2_TOP+2 and v_cntr_reg < REGION2_BOTTOM-2
- else bg_green;
-
- vga_blue <= I_data_M_vga_region1(7 downto 4) when h_cntr_reg > REGION1_LEFT+2 and h_cntr_reg < REGION1_RIGHT-2
- and v_cntr_reg > REGION1_TOP+2 and v_cntr_reg < REGION1_BOTTOM-2
- else I_data_M_vga_region2(7 downto 4) when h_cntr_reg > REGION2_LEFT+2 and h_cntr_reg < REGION2_RIGHT-2
- and v_cntr_reg > REGION2_TOP+2 and v_cntr_reg < REGION2_BOTTOM-2
- else bg_blue;
-
-
-
+
+ vga_red <= I_data_M_vga_region1(7 downto 4) when h_cntr_reg > REGION1_LEFT+2 and h_cntr_reg < REGION1_RIGHT-2
+ and v_cntr_reg > REGION1_TOP+2 and v_cntr_reg < REGION1_BOTTOM-2
+ else I_data_M_vga_region2(7 downto 4) when h_cntr_reg > REGION2_LEFT+2 and h_cntr_reg < REGION2_RIGHT-2
+ and v_cntr_reg > REGION2_TOP+2 and v_cntr_reg < REGION2_BOTTOM-2
+ else bg_red;
+
+ vga_green <= I_data_M_vga_region1(7 downto 4) when h_cntr_reg > REGION1_LEFT+2 and h_cntr_reg < REGION1_RIGHT-2
+ and v_cntr_reg > REGION1_TOP+2 and v_cntr_reg < REGION1_BOTTOM-2
+ else I_data_M_vga_region2(7 downto 4) when h_cntr_reg > REGION2_LEFT+2 and h_cntr_reg < REGION2_RIGHT-2
+ and v_cntr_reg > REGION2_TOP+2 and v_cntr_reg < REGION2_BOTTOM-2
+ else bg_green;
+
+ vga_blue <= I_data_M_vga_region1(7 downto 4) when h_cntr_reg > REGION1_LEFT+2 and h_cntr_reg < REGION1_RIGHT-2
+ and v_cntr_reg > REGION1_TOP+2 and v_cntr_reg < REGION1_BOTTOM-2
+ else I_data_M_vga_region2(7 downto 4) when h_cntr_reg > REGION2_LEFT+2 and h_cntr_reg < REGION2_RIGHT-2
+ and v_cntr_reg > REGION2_TOP+2 and v_cntr_reg < REGION2_BOTTOM-2
+ else bg_blue;
+
+
+
------------------------------------------------------------
-- Turn Off VGA RBG Signals if outside of the active screen
-- Make a 4-bit AND logic with the R, G and B signals
------------------------------------------------------------
- vga_red_cmb <= (active & active & active & active) and vga_red;
- vga_green_cmb <= (active & active & active & active) and vga_green;
- vga_blue_cmb <= (active & active & active & active) and vga_blue;
-
-
- -- Register Outputs
- process (pxl_clk)
- begin
- if (rising_edge(pxl_clk)) then
-
- v_sync_reg_dly <= v_sync_reg;
- h_sync_reg_dly <= h_sync_reg;
- vga_red_reg <= vga_red_cmb;
- vga_green_reg <= vga_green_cmb;
- vga_blue_reg <= vga_blue_cmb;
- end if;
- end process;
-
- -- Assign outputs
- VGA_HS_O <= h_sync_reg_dly;
- VGA_VS_O <= v_sync_reg_dly;
- VGA_RED_O <= vga_red_reg;
- VGA_GREEN_O <= vga_green_reg;
- VGA_BLUE_O <= vga_blue_reg;
-
-end Behavioral;
\ No newline at end of file
+ vga_red_cmb <= (active & active & active & active) and vga_red;
+ vga_green_cmb <= (active & active & active & active) and vga_green;
+ vga_blue_cmb <= (active & active & active & active) and vga_blue;
+
+
+ -- Register Outputs
+ process (pxl_clk)
+ begin
+ if (rising_edge(pxl_clk)) then
+
+ v_sync_reg_dly <= v_sync_reg;
+ h_sync_reg_dly <= h_sync_reg;
+ vga_red_reg <= vga_red_cmb;
+ vga_green_reg <= vga_green_cmb;
+ vga_blue_reg <= vga_blue_cmb;
+ end if;
+ end process;
+
+ -- Assign outputs
+ VGA_HS_O <= h_sync_reg_dly;
+ VGA_VS_O <= v_sync_reg_dly;
+ VGA_RED_O <= vga_red_reg;
+ VGA_GREEN_O <= vga_green_reg;
+ VGA_BLUE_O <= vga_blue_reg;
+
+end Behavioral;
--
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