diff --git a/src/Nexys4VideoA7_Sobel.xdc b/src/constraints/Nexys4VideoA7_Sobel.xdc
similarity index 100%
rename from src/Nexys4VideoA7_Sobel.xdc
rename to src/constraints/Nexys4VideoA7_Sobel.xdc
diff --git a/src/Nexys4_Sobel.xdc b/src/constraints/Nexys4_Sobel.xdc
similarity index 100%
rename from src/Nexys4_Sobel.xdc
rename to src/constraints/Nexys4_Sobel.xdc
diff --git a/src/dancing_spider.txt b/src/data/dancing_spider.txt
similarity index 100%
rename from src/dancing_spider.txt
rename to src/data/dancing_spider.txt
diff --git a/src/DualPortRamGeneric.vhd b/src/hdl/DualPortRamGeneric.vhd
similarity index 100%
rename from src/DualPortRamGeneric.vhd
rename to src/hdl/DualPortRamGeneric.vhd
diff --git a/src/SinglePortROMFileInitGeneric.vhd b/src/hdl/SinglePortROMFileInitGeneric.vhd
similarity index 100%
rename from src/SinglePortROMFileInitGeneric.vhd
rename to src/hdl/SinglePortROMFileInitGeneric.vhd
diff --git a/src/adrgenUnit.vhd b/src/hdl/adrgenUnit.vhd
similarity index 87%
rename from src/adrgenUnit.vhd
rename to src/hdl/adrgenUnit.vhd
index 04a955337c5103fb4d37978ccf04fbfd7b2d8734..bc334f9bcdd8edefefade18fe97564f4b8d8ef83 100644
--- a/src/adrgenUnit.vhd
+++ b/src/hdl/adrgenUnit.vhd
@@ -22,14 +22,12 @@ end adrgenUnit;
architecture Behavioral of adrgenUnit is
---
--- Write here your VHDL code
---
+__BLANK__
+
begin
---
--- Write here your VHDL code
---
+__BLANK__
+
end Behavioral;
diff --git a/src/automate.vhd b/src/hdl/automate.vhd
similarity index 77%
rename from src/automate.vhd
rename to src/hdl/automate.vhd
index affac4b059f1651ec2a17d20c278fc7623bb4e10..a2b9ec6632dc7c2e2dc84b44d61863c81cd03a2f 100644
--- a/src/automate.vhd
+++ b/src/hdl/automate.vhd
@@ -1,6 +1,6 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
+library ieee;
+use ieee.std_logic_1164.all;
entity automate is
port (
@@ -9,29 +9,28 @@ entity automate is
I_go : in std_logic;
I_EndImage : in std_logic;
I_NewLine : in std_logic;
- -- signaux de commandes vers l'unit� op�rative
+ -- signaux de commandes vers l'unit� op�rative
O_ldPix11 : out std_logic;
O_ldPix21 : out std_logic;
O_ldPix31 : out std_logic;
O_shReg : out std_logic;
O_ldPixEdge : out std_logic;
- -- signaux de commandes vers le g�n�rateur d'adresses
+ -- signaux de commandes vers le g�n�rateur d'adresses
O_clr_PtrLine : out std_logic;
O_inc_PtrLine : out std_logic;
O_clr_PtrCol : out std_logic;
O_inc_PtrCol : out std_logic;
O_selPix : out std_logic_vector (1 downto 0);
- -- signaux de commandes vers les m�moires
+ -- signaux de commandes vers les m�moires
O_enM_R : out std_logic;
O_enM_W : out std_logic;
- -- signal de commande vers le contr�leur VGA
+ -- signal de commande vers le contr�leur VGA
O_StartDisplay : out std_logic
);
end automate;
architecture Behavioral of automate is
--- d�finir un type �num�r� avec les �tats de la FSM et deux signaux de ce type
type automate_state_type is (Idle, Init, Pix1, Pix2, Pix3, sh1, Pix4, Pix5,
Pix6, sh2, Pix7, Pix8, Pix9, Exec, OutEdge,
sh3, EndSobel);
@@ -72,11 +71,11 @@ begin
case current_state is
when Idle =>
- -- calcul des sorties SPECIFIQUES � l'�tat
+ -- calcul des sorties SPECIFIQUES � l'�tat
O_clr_PtrLine <= I_go;
O_clr_PtrCol <= I_go;
- -- calcul de l'�tat suivant
+ -- calcul de l'�tat suivant
if(I_go = '1') then
next_state <= Init;
else
@@ -84,11 +83,11 @@ begin
end if;
when Init =>
- -- calcul des sorties SPECIFIQUES � l'�tat
+ -- calcul des sorties SPECIFIQUES � l'�tat
O_enM_R <= '1';
O_selPix <= "00";
- -- calcul de l'�tat suivant
+ -- calcul de l'�tat suivant
if(I_EndImage = '0') then
next_state <= Pix1;
else
@@ -96,12 +95,12 @@ begin
end if;
when Pix1 =>
- -- calcul des sorties SPECIFIQUES � l'�tat
+ -- calcul des sorties SPECIFIQUES � l'�tat
O_ldPix11 <= '1';
O_enM_R <= '1';
O_selPix <= "01";
- -- calcul de l'�tat suivant
+ -- calcul de l'�tat suivant
next_state <= Pix2;
when Pix2 =>
@@ -109,9 +108,8 @@ begin
---
--- Write here your VHDL code
---
+__BLANK__
+
diff --git a/src/gradientUnit.vhd b/src/hdl/gradientUnit.vhd
similarity index 70%
rename from src/gradientUnit.vhd
rename to src/hdl/gradientUnit.vhd
index 9619d8e55e61d10a4d5a3a520a5c368a29e9fffe..58f5268f10478b3c2787413d3794e7ce32dd7b57 100644
--- a/src/gradientUnit.vhd
+++ b/src/hdl/gradientUnit.vhd
@@ -1,7 +1,7 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
entity gradientUnit is
port (I_Pix11, I_Pix12, I_Pix13 : in std_logic_vector (7 downto 0);
@@ -14,14 +14,12 @@ end gradientUnit;
architecture Behavioral of gradientUnit is
---
--- Write here your VHDL code
---
+__BLANK__
+
begin
---
--- Write here your VHDL code
---
+__BLANK__
+
end Behavioral;
diff --git a/src/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
similarity index 100%
rename from src/operativeUnit.vhd
rename to src/hdl/operativeUnit.vhd
diff --git a/src/pixedgeReg.vhd b/src/hdl/pixedgeReg.vhd
similarity index 78%
rename from src/pixedgeReg.vhd
rename to src/hdl/pixedgeReg.vhd
index 3fdce0a76732f4c093d157ced909bdf305b5d3ab..86b97ffa397e32c788130e1fcc7453174dbfd996 100644
--- a/src/pixedgeReg.vhd
+++ b/src/hdl/pixedgeReg.vhd
@@ -14,14 +14,12 @@ end pixedgeReg;
architecture Behavioral of pixedgeReg is
---
--- Write here your VHDL code
---
+__BLANK__
+
begin
---
--- Write here your VHDL code
---
+__BLANK__
+
end Behavioral;
diff --git a/src/regUnit.vhd b/src/hdl/regUnit.vhd
similarity index 89%
rename from src/regUnit.vhd
rename to src/hdl/regUnit.vhd
index 4f30b476b72c6fe5a6f8466fa278ca76d4507b76..3e3e0a0b89a2cfe06d3380e93a365f9cf4a2c37d 100644
--- a/src/regUnit.vhd
+++ b/src/hdl/regUnit.vhd
@@ -1,7 +1,7 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
entity regUnit is
port (I_clk : in std_logic;
@@ -29,9 +29,7 @@ begin
begin
if(rising_edge(I_clk)) then
---
--- Write here your VHDL code
---
+__BLANK__
end if;
end process;
diff --git a/src/sobelProc.vhd b/src/hdl/sobelProc.vhd
similarity index 100%
rename from src/sobelProc.vhd
rename to src/hdl/sobelProc.vhd
diff --git a/src/sobelSys.vhd b/src/hdl/sobelSys.vhd
similarity index 100%
rename from src/sobelSys.vhd
rename to src/hdl/sobelSys.vhd
diff --git a/src/tb_adrgenUnit.vhd b/src/hdl/tb_adrgenUnit.vhd
similarity index 100%
rename from src/tb_adrgenUnit.vhd
rename to src/hdl/tb_adrgenUnit.vhd
diff --git a/src/tb_automate.vhd b/src/hdl/tb_automate.vhd
similarity index 100%
rename from src/tb_automate.vhd
rename to src/hdl/tb_automate.vhd
diff --git a/src/tb_gradientUnit.vhd b/src/hdl/tb_gradientUnit.vhd
similarity index 100%
rename from src/tb_gradientUnit.vhd
rename to src/hdl/tb_gradientUnit.vhd
diff --git a/src/tb_operativeUnit.vhd b/src/hdl/tb_operativeUnit.vhd
similarity index 100%
rename from src/tb_operativeUnit.vhd
rename to src/hdl/tb_operativeUnit.vhd
diff --git a/src/tb_regUnit.vhd b/src/hdl/tb_regUnit.vhd
similarity index 100%
rename from src/tb_regUnit.vhd
rename to src/hdl/tb_regUnit.vhd
diff --git a/src/tb_sobelProc.vhd b/src/hdl/tb_sobelProc.vhd
similarity index 100%
rename from src/tb_sobelProc.vhd
rename to src/hdl/tb_sobelProc.vhd
diff --git a/src/tb_sobelSys.vhd b/src/hdl/tb_sobelSys.vhd
similarity index 100%
rename from src/tb_sobelSys.vhd
rename to src/hdl/tb_sobelSys.vhd
diff --git a/src/vga_nexys4_2regions.vhd b/src/hdl/vga_nexys4_2regions.vhd
similarity index 100%
rename from src/vga_nexys4_2regions.vhd
rename to src/hdl/vga_nexys4_2regions.vhd